RTAX250SL-1CG624E vs RTAX250SL-1LG624V Comparación
Comparación detallada lado a lado de RTAX250SL-1CG624E por Microchip Technology y RTAX250SL-1LG624V por Microchip Technology. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Microchip Technology
RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip
RTAX250SL-1CG624E ✓ ActivoMicrochip Technology
RTAX250SL-1LG624V - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-1LG624V ✓ ActivoComparación de especificaciones
| Parámetro | RTAX250SL-1CG624E | RTAX250SL-1LG624V |
|---|---|---|
| Marca | Microchip Technology | Microchip Technology |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1,00 | $950,00 |
| Equivalent System Gates | 250,000 gates | 250,000 gates |
| Configurable Logic Blocks (CLBs) | 2816 | 2816 |
| Logic Cells | 4224 | 4224 |
| User I/O | 248 inputs / 248 outputs | — |
| Core Supply Voltage | 1.5 V (1.425 V to 1.575 V) | 1.5 V nominal |
| Maximum Combinatorial Delay (CLB) | 0.93 ns | — |
| Maximum System Frequency | 649 MHz | — |
| Process Technology | 0.15 um CMOS | — |
| Logic Family | CMOS | — |
| Encapsulado | 624-ball Ceramic Column Grid Array (CCGA-624) | 624-terminal ceramic CGA (LG624), 1.270 mm terminal pitch |
| Temperatura de funcionamiento | -55C to +125C | -55C to +125C |
| Radiation Tolerance | SEU-immune to specified LET threshold; SEU rate < 10-10 errors/bit-day | — |
| SEU Mitigation | SEU-hardened registers (no external TMR required) | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Configuration | Live-at-power-up, true single-chip operation | — |
| Tipo de montaje | Surface Mount (ceramic column grid array) | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| I/O Supply Voltage | [DATA_NEEDED: I/O bank voltage] | — |
| Architecture | — | CMOS antifuse (Axcelerator-derived) |
| Family | — | RTAX-S/SL Radiation-Tolerant FPGA |
| Speed Grade | — | -1 |
| Configuration Type | — | One-Time Programmable (antifuse) |
| Clock Resources | — | Segmentable clocks, chip-wide highway routing |
| Arithmetic Support | — | Dedicated carry logic |
| Application Domain | — | Space-flight systems |
| Total Ionizing Dose Tolerance | — | [DATA_NEEDED: TID level] |