SI5345A-D-GMR vs SI5345A-D10713-GM Comparación
Comparación detallada lado a lado de SI5345A-D-GMR por Skyworks Solutions y SI5345A-D10713-GM por Skyworks Solutions. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Skyworks Solutions
SI5345A-D-GMR - 10-Output Jitter Attenuator | Skyworks | 1028 MHz
SI5345A-D-GMR ✓ ActivoSkyworks Solutions
SI5345A-D10713-GM - 10-Output Jitter Attenuator | Skyworks
SI5345A-D10713-GM ✓ ActivoComparación de especificaciones
| Parámetro | SI5345A-D-GMR | SI5345A-D10713-GM |
|---|---|---|
| Marca | Skyworks Solutions | Skyworks Solutions |
| Categoría | Clock & Timing | Clock & Timing |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,75 | $19,95 |
| Product Type | Clock Multiplier / Jitter Attenuator | Clock Multiplier / Jitter Attenuator |
| Series | Si5345 (Si5345A variant, Rev D) | — |
| Número de salidas | 10 | 10 |
| Output Frequency Range | 0.001 MHz to 1028 MHz | 1 Hz to 1028 MHz |
| Input Frequency Range | 0.008 MHz to 750 MHz | — |
| RMS Jitter (12 kHz-20 MHz) | 1.5 ps max (typ < 200 fs) | — |
| Output Logic Levels | LVPECL, LVDS, HCSL, LVCMOS, CML (per-pin selectable) | — |
| PLL Technology | DSPLL (4th-gen) + MultiSynth fractional divider | — |
| Programming Interface | I2C / SPI (selectable) | — |
| Non-Volatile Memory | Yes (in-circuit programmable) | — |
| Encapsulado | 64-pin QFN (9x9 mm) with exposed pad | 64-VFQFN Exposed Pad (9 mm x 9 mm) |
| Tipo de montaje | Surface Mount | — |
| Tensión de alimentación | 1.8 V core, 3.3 V I/O (typical) | 3.3 V core, configurable output supply domains |
| Temperatura de funcionamiento | -40 C to +85 C | — |
| Nivel MSL | 3 | MSL3 / 3 (per JEDEC J-STD-020) |
| Estado RoHS | Compliant | Compliant |
| Configuration Tool | ClockBuilder Pro (Skyworks / Silicon Labs) | ClockBuilder Pro |
| Maximum Output Frequency | — | 1028 MHz |
| Input Reference Frequency Range | — | 1 Hz to 750 MHz (per datasheet family) |
| Number of Independent DSPLL Lanes | — | 4 |
| Typical RMS Jitter (12 kHz to 20 MHz) | — | < 100 fs (Si5345 family typical) |
| Control Interface | — | I2C / SPI |
| On-Chip EEPROM | — | Yes (factory programmed with -Dxxxxx frequency plan) |
| Output Types | — | Differential (LVPECL, LVDS, HCSL, CML) and single-ended CMOS |
| Jitter Attenuation Bandwidth | — | Digitally programmable, 0.1 Hz to 4 kHz |
| Reference Inputs | — | Up to 2 references with hitless switching and holdover |
| Rango de temperatura de funcionamiento | — | -40C to +85C (industrial grade) |