AD679KN - 14-Bit 128 kSPS Sampling ADC | Analog Devices
N.º de pieza: AD679KN ✗ Fin de vida| Cant. | Precio unitario | Total |
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| 1 | $0 | $0,00 |
| 10 | $0 | $0,00 |
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| 500 | $0 | $0,00 |
| 1.000 | $0 | $0,00 |
AD679KN Descripción general
An ADC is a data-acquisition building block that converts an analog voltage into a digital code. The AD679 belongs to the integrated-circuit hierarchy: ADC, data converter, signal-processing IC, and semiconductor. Its complete sampling architecture reduces the number of external analog components required for a basic measurement channel, while the integrated reference and clock circuitry simplify system design. Analog Devices states that the AD679 shares the same pinout as the AD678 12-bit, 200 kSPS ADC, which can assist upgrade-path planning when board space and interface requirements remain compatible.
The principal verified specifications are 14-bit resolution and 128 kSPS throughput. The AD679 family is specified for AC or dynamic parameters, including signal-to-noise plus distortion, THD, and IMD, making it appropriate for waveform capture, instrumentation, communications, and industrial measurement. The verified product data identifies AD679KN as a commercial-temperature, through-hole, 28-pin DIP variant. The manufacturer also documents versions compliant with MIL-STD-883, but the provided data does not establish that the AD679KN suffix itself is that compliant version.
The device combines sampling and conversion functions in one monolithic converter. This integration can simplify analog front-end design compared with a discrete sample-and-hold stage followed by a separate ADC. Designers must still establish the input range, acquisition time, reference behavior, digital interface timing, grounding, and signal-conditioning requirements from the complete manufacturer datasheet before finalizing a circuit.
Typical applications include industrial process measurement, audio and waveform instrumentation, communications receivers, laboratory data acquisition, and embedded control systems. In each case, the 128 kSPS sampling rate limits the bandwidth that can be represented without aliasing, while the 14-bit code width sets the quantization resolution. Input filtering and anti-alias design are therefore central to obtaining useful dynamic performance.
A key design consideration is that the ADC’s dynamic specifications must be interpreted at the operating conditions and test bandwidth specified by Analog Devices. Do not infer guaranteed SNR, THD, input range, or acquisition time from the distributor snippets; consult the official datasheet and validate the complete analog and digital interface on hardware.
This page consolidates the verified AD679KN identity, manufacturer upgrade-path information, distributor listing details, and engineering-focused application guidance. It also makes clear where verified data is insufficient, so engineers can request the missing electrical limits before committing to a design.
Alternativas directas para AD679KN — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
AD679JNZ
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
AD679JN
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
AD679K
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
AD679B
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
AD679T
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
AD679KN Valores máximos y características eléctricas
| Converter Type | Complete sampling ADC |
| Resolución | 14 bit |
| Frecuencia de muestreo | 128 kSPS |
| Architecture | Monolithic sampling ADC |
| Integrated Sample-and-Hold Amplifier | Yes |
| Integrated Voltage Reference | Yes |
| Integrated Clock Generation | Yes |
| Digital Interface | Microprocessor-compatible bus interface |
| Dynamic Performance Parameters | S/N+D ratio, THD, and IMD |
| Encapsulado | 28-pin DIP |
| Tipo de montaje | Through-hole |
| Terminal Count | 28 |
| Temperature Grade | Commercial |
| Upgrade Path | Same pinout as the 12-bit, 200 kSPS AD678 ADC |
| Military Version Availability | AD679 versions compliant with MIL-STD-883 are available |
Guía de configuración de pines de AD679KN 28-pin dip
Configuración de pines para AD679KN (encapsulado 28-pin dip). Este componente analógico presenta pines de entrada, salida y alimentación. Consulte la hoja de datos del fabricante para conocer las configuraciones de los pines de ajuste de offset, compensación y habilitación. Ideal para circuitos de acondicionamiento de señal y amplificadores.
No hay datos detallados de patillaje disponibles para AD679KN.
Consulte la hoja de datos para ver la configuración completa de patillas.
Aplicaciones típicas
AD679KN es adecuado para 7 aplicacións: Industrial Process Measurement, Waveform Data Acquisition, Communications Receiver, Audio Measurement, Laboratory Instrumentation, Embedded Control Data Acquisition, Test and Measurement Signal Capture.
Industrial Process Measurement
The AD679KN fits industrial process-measurement channels that require a complete sampling ADC rather than a converter requiring a separate sample-and-hold stage. Its verified 14-bit resolution and 128 kSPS throughput provide a defined starting point for digitizing sensor signals, while the integrated reference and clock circuitry can simplify the analog front end. A practical design should place the converter behind conditioning, protection, and anti-alias filtering, then verify the full signal chain against the required accuracy. The supplied data does not specify input range, SNR, THD, or operating-temperature limits, so those values must come from the current Analog Devices datasheet before production release.
Recomendado
Waveform Data Acquisition
The AD679KN is suitable as the conversion element in a waveform-acquisition system requiring 14-bit data and a 128 kSPS sampling rate. Its complete sampling architecture integrates the sample-and-hold amplifier, reference, and clock-generation circuitry, reducing the number of separate blocks that must be coordinated. The system designer should select the analog input range, acquisition settling behavior, and output timing from the official datasheet, then apply an anti-alias filter before the ADC. Dynamic results should be compared at the same signal level and bandwidth because the verified source identifies S/N+D ratio, THD, and IMD as relevant family specifications but gives no numerical test results.
Recomendado
Communications Receiver
The AD679KN can support communications receiver and demodulation front ends where sampled I/Q or envelope information is needed at a moderate rate. The 128 kSPS throughput provides a concrete upper sampling limit, while 14-bit quantization gives 16,384 nominal code levels for representing an analog waveform. That theoretical code count does not guarantee full system accuracy because reference error, analog noise, acquisition time, filtering, and clock quality also contribute. Use the converter’s specified dynamic performance and digital timing, and preserve sufficient guard band around the retained signal band to prevent aliasing.
Recomendado
Audio Measurement
The AD679KN may be used in audio test equipment when a 14-bit, 128 kSPS measurement channel is sufficient for the required bandwidth and dynamic range. The integrated voltage reference and clock circuitry can help reduce external circuitry, but audio performance still depends on the input conditioning, reference quality, clock jitter, grounding, and anti-alias filter. The verified manufacturer material specifically highlights S/N+D ratio, THD, and IMD as dynamic parameters, making those measurements central to validation. Do not market the device as a fixed THD or SNR grade until the exact AD679KN operating conditions and test results are confirmed from Analog Devices documentation.
Recomendado
Laboratory Instrumentation
The AD679KN is a reasonable candidate for laboratory instruments that digitize controlled analog signals and need a compact, integrated conversion function. Its 28-pin through-hole DIP package supports prototyping and socketed or hand-soldered laboratory assemblies, while the 14-bit resolution provides more code levels than an 8-bit or 12-bit system. The instrument designer must still define analog input scaling, reference behavior, clock source, control-interface timing, calibration, and measurement bandwidth. Because the verified data lacks minimum input voltage, acquisition time, and accuracy limits, these values should be treated as design gates rather than assumed from the nominal sampling rate.
Recomendado
Embedded Control Data Acquisition
The AD679KN can serve as an ADC peripheral in an embedded controller design when the system needs more resolution and a higher sample rate than a basic control ADC provides. Its microprocessor-compatible bus interface is explicitly identified in the verified family description, allowing a controller or programmable logic device to retrieve conversion results. The external microcontroller must match the ADC’s electrical interface, timing, control levels, and data format, which are not supplied in the verified snippets. Firmware should also handle conversion completion, overrun conditions, calibration, and any reference or clock configuration supported by the exact datasheet.
Recomendado
Test and Measurement Signal Capture
The AD679KN can be integrated into a test-and-measurement signal-capture front end when the required conversion rate is 128 kSPS or lower and 14-bit resolution is useful. The integrated sample-and-hold amplifier, voltage reference, and clock-generation blocks provide a useful foundation for a repeatable measurement channel. The instrument should calibrate offset, gain, reference behavior, and linearity using the manufacturer’s specified procedures, while the analog path should provide sufficient settling time and rejection of out-of-band noise. The verified data does not provide calibration coefficients or guaranteed accuracy, so production limits must be derived from the official datasheet and measured hardware.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para AD679KN — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | AD679JNZ | AD679JN | AD679K | AD679B | AD679T |
|---|---|---|---|---|---|---|
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Sampling Rate | 128 kSPS | 128 kSPS | 128 kSPS | 128 kSPS | 128 kSPS | 128 kSPS |
| Converter Function | Complete sampling ADC | AD679 family converter | AD679 family converter | AD679 family converter | AD679 family converter | AD679 family converter |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Integrated Sample-and-Hold | Yes | Yes | Yes | Yes | Yes | Yes |
| Integrated Voltage Reference | Yes | Yes | Yes | Yes | Yes | Yes |
Diferenciadores clave
- Complete integrated sampling architecture (frente a AD679JNZ)
- Documented pinout relationship with AD678 (frente a AD679JNZ)
- Integrated reference and clock-generation circuitry (frente a AD679JN)
- AD678 upgrade path (frente a AD679K)
Notas de diseño
Design the input path around the AD679KN’s acquisition and settling requirements rather than treating the 128 kSPS headline rate as a complete bandwidth specification. Place the protection, gain, buffer, and anti-alias stages close enough to the ADC to minimize parasitic capacitance and reflection. The verified data does not state input capacitance, acquisition time, or input bandwidth; use the manufacturer’s timing diagram and layout guidance before selecting series resistance, capacitor values, or buffer bandwidth.
Use a stable analog and digital grounding strategy and keep the converter’s reference and clock connections away from high-current switching paths. Decouple the supply according to the official datasheet, and route clock and data lines with attention to return paths. Because the AD679KN is a 28-pin through-hole DIP, allow for lead clearance, socket compatibility, thermal airflow, and analog input routing around the package. Confirm the exact mechanical drawing before finalizing the board footprint.
Do not treat the AD679’s documented same-pinout relationship with the AD678 as proof that every suffix is a drop-in replacement. The AD678 is identified as a 12-bit, 200 kSPS device, while AD679KN is a 14-bit, 128 kSPS part. Check supply voltage, input range, timing, data coding, control signals, and package suffix in the current datasheet. Also do not infer AD679KN MIL-STD-883 qualification from the statement that compliant AD679 versions are available.
Establish the ADC power budget before choosing the system supply. The converter includes reference and clock circuitry, so supply noise and grounding can affect dynamic performance even when the nominal sampling rate is met. The verified snippets do not provide supply voltage, current, reference voltage, or power dissipation; those values are required for thermal and power-supply design. Use the exact AD679KN datasheet values and include startup, reference settling, and digital-output transitions in system calculations.
Información de cumplimiento
The verified sources identify the AD679 family and mention versions compliant with MIL-STD-883, but they do not provide AD679KN-specific RoHS, REACH, lead-free, halogen-free, or conflict-minerals declarations. Automotive qualification is not applicable to the supplied data; military compliance must be verified for the exact ordering code.
