AD9051BRSRL-2V - 10-Bit 60 MSPS ADC, 28-SSOP | Analog Devices
N.º de pieza: AD9051BRSRL-2V ✗ Fin de vida| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.25 | $162,50 |
| 100 | $14.1 | $1.410,00 |
| 500 | $12.4 | $6.200,00 |
| 1.000 | $10.95 | $10.950,00 |
AD9051BRSRL-2V Descripción general
An analog-to-digital converter is a data-acquisition building block that converts a continuous-time analog input into a discrete digital code at a sampling clock rate, and belongs to the broader hierarchy of mixed-signal IC -> ADC -> pipelined/flash ADC -> semiconductor. The two-step (sub-ranging) architecture used in the AD9051 is optimized to deliver the best dynamic performance available while still keeping total power dissipation low, which makes it a popular choice for cost-driven designs that still need solid spurious-free dynamic range and signal-to-noise ratio.
Key specifications include 60 MSPS sampling rate, 9.3 effective number of bits (ENOB) at fIN = 10.3 MHz, 250 mW total power consumption at 60 MSPS, a user-selectable input bandwidth of either 50 MHz or 130 MHz, and on-chip track-and-hold plus voltage reference. The internal T/H relaxes front-end analog driver requirements and the integrated reference eliminates an external reference component, reducing both BOM count and board area in cost-sensitive designs.
Typical applications for the AD9051BRSRL-2V include digital video, professional CCD imaging, digital oscilloscopes, low-cost digital still cameras, portable instrumentation, and IF-sampling communication receivers where the selectable input bandwidth simplifies front-end anti-alias filter design. When laying out the PCB, keep the analog input traces short and use a solid ground plane; the encode clock should be routed with controlled impedance and kept away from the analog inputs to preserve SNR.
Alternativas directas para AD9051BRSRL-2V — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con AD9051BRSRL-2V (mismo factor de forma y huella) — difiere en Package, Architecture, Packaging, Sampling Rate, Data Interface.
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AD9051BRSRL-2V
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AD9051BRSZRL-2V
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AD9051BRSRL
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Ver hoja de datos →AD9051BRSRL-2V Valores máximos y características eléctricas
| Number of Bits | 10 |
| Sampling Rate (Per Second) | 60 MSPS |
| Number of Inputs | 1 |
| Input Type | Single-ended |
| Data Interface | Parallel |
| Architecture | Two-step (sub-ranging) pipelined |
| Effective Number of Bits (ENOB) | 9.3 bits at fIN = 10.3 MHz |
| Analog Supply Voltage | +5 V |
| Digital Logic Compatibility | 5 V or 3 V CMOS outputs, TTL-compatible encode clock |
| Total Power Dissipation | 250 mW at 60 MSPS |
| Selectable Input Bandwidth | 50 MHz or 130 MHz (user-selectable) |
| On-Chip Functions | Track-and-hold amplifier, voltage reference |
| Encapsulado | 28-SSOP (5.30 mm body width) |
| Packaging | Tape & Reel (TR), 7-inch reel |
| Rango de temperatura de funcionamiento | -40C to +85C (industrial) |
| Tipo de montaje | Surface Mount |
Configuración de pines de AD9051BRSRL-2V
| Pin 1 | AVDD — +5 V analog supply |
| Pin 2 | AIN — Analog input |
| Pin 3 | AGND — Analog ground |
| Pin 4 | VREF — Internal voltage reference (decoupling) |
| Pin 5 | AGND — Analog ground |
| Pin 6 | BW_SEL — Input bandwidth select (50 MHz / 130 MHz) |
| Pin 7 | ENCODE — TTL-compatible encode clock input |
| Pin 8 | DGND — Digital ground |
| Pin 9 | DVDD — +5 V (or 3 V) digital supply |
| Pin 10 | D9 (MSB) — Parallel CMOS data output bit 9 |
| Pin 11 | D8 — Parallel CMOS data output bit 8 |
| Pin 12 | D7 — Parallel CMOS data output bit 7 |
| Pin 13 | D6 — Parallel CMOS data output bit 6 |
| Pin 14 | D5 — Parallel CMOS data output bit 5 |
| Pin 15 | D4 — Parallel CMOS data output bit 4 |
| Pin 16 | D3 — Parallel CMOS data output bit 3 |
| Pin 17 | D2 — Parallel CMOS data output bit 2 |
| Pin 18 | D1 — Parallel CMOS data output bit 1 |
| Pin 19 | D0 (LSB) — Parallel CMOS data output bit 0 |
| Pin 20 | DRVDD — Output driver supply |
| Pin 21 | AGND — Analog ground |
| Pin 22 | NC — Not connected |
| Pin 23 | NC — Not connected |
| Pin 24 | NC — Not connected |
| Pin 25 | NC — Not connected |
| Pin 26 | NC — Not connected |
| Pin 27 | NC — Not connected |
| Pin 28 | NC — Not connected |
Aplicaciones típicas
AD9051BRSRL-2V es adecuado para 6 aplicacións: Digital Oscilloscope Front-End, Professional CCD Imaging Systems, Digital Video Broadcast Equipment, IF-Sampling Communication Receivers, Portable Instrumentation and Data Acquisition, Digital Still Camera Image Pipeline.
Digital Oscilloscope Front-End
The AD9051BRSRL-2V's 60 MSPS sample rate and 9.3 ENOB at 10.3 MHz input make it a strong fit for entry-level digital oscilloscope front-ends. The 130 MHz selectable input bandwidth supports undersampling of periodic signals beyond Nyquist, while the 50 MHz setting improves SNR on slower baseband waveforms. The integrated T/H and reference cut BOM count for cost-sensitive scopes, and the CMOS/TTL digital outputs feed directly into an FPGA or display controller without level translation. Designers should keep analog input traces matched and route the encode clock with controlled impedance to preserve the part's 60 dB-class SNR.
Recomendado
Professional CCD Imaging Systems
In CCD imaging applications, the AD9051BRSRL-2V digitizes the analog output of a multi-megapixel CCD at pixel-clock rates up to 60 MSPS while maintaining 9.3 effective bits at 10.3 MHz, preserving dynamic range for color grading and post-processing. The 28-SSOP footprint keeps the converter close to the analog front-end to minimize trace noise, and the +5 V single supply simplifies the analog/digital supply architecture in a camera head. The integrated track-and-hold relaxes the bandwidth requirements on the CCD output buffer, and the on-chip voltage reference removes a drift source from black-level calibration.
Recomendado
Digital Video Broadcast Equipment
The AD9051BRSRL-2V serves as a low-cost 10-bit video ADC for SDTV and early HDTV broadcast equipment, where 60 MSPS exceeds the 27 MSPS required for SD-SDI and supports the 54 MHz 4:2:2 component format. The CMOS/TTL outputs drive video processing ASICs without additional logic-level shifters, while the single +5 V supply matches legacy analog rails still common in broadcast infrastructure. The 130 MHz input bandwidth cleanly passes component YPbPr signals, and the 50 MHz setting can be selected for luminance-only channels to maximize SNR.
Recomendado
IF-Sampling Communication Receivers
In IF-sampling receiver designs, the AD9051BRSRL-2V's 130 MHz selectable input bandwidth allows engineers to digitize an IF stage directly, eliminating a downconversion mixer and SAW filter. The 60 MSPS sample rate supports up to 30 MHz of usable baseband after digital I/Q demodulation, suitable for narrowband land-mobile and fixed-wireless links. The 9.3 ENOB preserves link SNR for digital demodulators, and the 28-SSOP industrial-temp package (-40C to +85C) tolerates outdoor base-station thermal environments. Designers should use the 50 MHz mode when narrower IF bandwidth is acceptable to gain extra SNR margin.
Recomendado
Portable Instrumentation and Data Acquisition
Battery-powered portable instruments benefit from the AD9051BRSRL-2V's 250 mW total power dissipation at 60 MSPS, which extends runtime when the part is duty-cycled. The on-chip track-and-hold and voltage reference shrink the analog BOM, freeing board area for batteries, displays, or wireless radios. The 28-SSOP industrial-temp rating supports handheld oscilloscope, multimeter, and data-logger enclosures that may see cold-field or hot-solar conditions. The CMOS digital outputs allow direct interface to a low-power FPGA or ARM Cortex-M controller running the display and USB stack.
Recomendado
Digital Still Camera Image Pipeline
In early-generation digital still cameras, the AD9051BRSRL-2V provides 10-bit conversion of the sensor analog front-end at pixel clock rates up to 60 MSPS, suiting 3-megapixel-plus sensors at video preview frame rates. The integrated reference and T/H remove two precision analog components from the BOM, critical for a consumer price point. The single +5 V supply aligns with the camera's analog rail, and the CMOS outputs connect directly to the image-processing ASIC without level shifters. The 50 MHz mode can be used for preview-stream downsampling to maximize dynamic range in low-light scenes.
Recomendado
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Datos de referencia de ingeniería para AD9051BRSRL-2V — comparación, orientación de diseño e información de cumplimiento.
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Comparación con alternativas
| Parámetro | Este producto | AD9051BRSRL-2V | AD9051BRSZ-2V | AD9051BRSZRL-2V | AD9051BRSRL | AD9051BRS |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices - same | Analog Devices - same | Analog Devices - same | Analog Devices - same | Analog Devices - same |
| Package | 28-SSOP | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits | 10 bits | 10 bits |
| Sample Rate | 60 MSPS | 60 MSPS | 60 MSPS | 60 MSPS | 60 MSPS | 60 MSPS |
| ENOB at 10.3 MHz | 9.3 bits | 9.3 bits | 9.3 bits | 9.3 bits | 9.3 bits | 9.3 bits |
| Power Dissipation | 250 mW at 60 MSPS | 250 mW | 250 mW | 250 mW | 250 mW | 250 mW |
| Input Bandwidth (selectable) | 50 MHz / 130 MHz | 50 MHz / 130 MHz | 50 MHz / 130 MHz | 50 MHz / 130 MHz | 50 MHz / 130 MHz | 50 MHz / 130 MHz |
| Supply Voltage | +5 V (digital 5 V or 3 V) | +5 V | +5 V | +5 V | +5 V | +5 V |
| Packaging Format | Tape & Reel (7-inch) | Tape & Reel (7-inch) - same | Tray | Reel (alternate size) | Tape & Reel (7-inch) | Tube |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Diferenciadores clave
- Single 5 V supply with on-chip T/H and reference (frente a AD9050BR)
- User-selectable 50 MHz / 130 MHz input bandwidth (frente a Generic 10-bit 60 MSPS ADC)
- CMOS outputs configurable for 5 V or 3 V logic (frente a Legacy TTL-only 10-bit ADC)
Notas de diseño
Route the analog input trace as a 50 ohm-controlled impedance microstrip, keep it short, and place the input decoupling capacitor within 2-3 mm of the AVDD pin. Use a continuous unbroken analog ground plane under the ADC and isolate it from the digital ground plane, joining the two only at the ADC's AGND pin to avoid ground-loop noise coupling into the analog input.
The encode clock must be a clean TTL-level square wave with < 200 ps jitter; route it on the digital side of the board with controlled impedance and place a small series damping resistor (22-33 ohm) near the ENCODE pin to damp overshoot. Keep the clock trace well separated from the analog input and AVDD traces; crossing should be at 90 degrees only. The bandwidth-select pin (BW_SEL) must be tied high (130 MHz) or low (50 MHz) directly to a logic rail, never left floating.
Estimated: at 60 MSPS continuous sampling, the AD9051BRSRL-2V draws roughly 250 mW from the +5 V analog supply. Place a 10 uF tantalum and a 0.1 uF ceramic bypass on each AVDD pin, and an identical pair on each DVDD/DRVDD pin. The internal voltage reference (VREF) requires a 0.1 uF ceramic decoupling cap close to the pin; do not load VREF with anything other than this cap or the internal reference noise will degrade ENOB.
Do not leave any of the digital output bits (D0-D9) floating - tie unused bits through a 10 kohm resistor to DGND to prevent coupling noise into adjacent outputs. The encode clock must be present before the analog input rises above 0 V; otherwise internal pipeline state is undefined and the first 2-3 samples after clock start should be discarded. Avoid driving the analog input above AVDD or below AGND - the ESD clamps are not designed for continuous overdrive and ENOB will suffer.
Información de cumplimiento
RoHS-compliant per distributor listings; AEC-Q100 not qualified (industrial temp only); lead-free confirmed; halogen-free status not explicitly stated in available data.