AR8031-AL1B-R - 10/100/1000 Ethernet PHY RGMII/SGMII | Qualcomm
N.º de pieza: AR8031-AL1B-R ✗ Fin de vida| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $3.43 | $3,43 |
| 10 | $3.09 | $30,90 |
| 100 | $2.65 | $265,00 |
| 500 | $2.31 | $1.155,00 |
| 1.000 | $2.05 | $2.050,00 |
AR8031-AL1B-R Descripción general
What is an Ethernet PHY? An Ethernet Physical Layer transceiver (PHY) is the analog front-end device that connects a digital Media Access Controller (MAC) to the copper or fiber Ethernet medium. Within the OSI model, the PHY sits at Layer 1 and handles line coding, link training, echo/NEXT cancellation, adaptive equalization, clock/data recovery, and auto-negotiation. The PHY is a category under Ethernet transceivers -> interface ICs -> integrated circuits, and serves as the physical gateway between a processor's MAC and the RJ-45 magnetics.
The AR8031-AL1B-R key features include 1 Gbps throughput, RGMII v2.0 and 1000BASE-X/SGMII MAC-side interfaces, 25 mV receiver hysteresis, automatic direction control (auto-MDI/MDIX), EEE 802.3az support, and hardware-accelerated 1588v2 / 802.1AS timestamping. It combines an echo canceller, NEXT canceller, feed-forward equalizer, joint Viterbi decoder, feedback equalizer, and timing-recovery DSP to enhance signal performance in noisy backplane and cable environments.
The device integrates a 1.2V core LDO, 1.0V VDDIO LDO, and supports 3.15V to 3.45V analog supply. The exposed thermal pad QFN-48 package provides low thermal resistance (typical 28 C/W with a 4-layer JEDEC JESD51 PCB), and 4 kV HBM ESD protection on the MDI pins protects against handling and cable-discharge transients.
Typical applications include industrial Ethernet switches, routers and gateways, automotive infotainment Ethernet PHYs (with NXP i.MX SoCs), 5G small-cell baseband backhaul, IP cameras / surveillance NVR, and printer/MFP embedded networking where a small footprint, low BOM, and integrated magnetics-termination are required.
Design consideration: The AR8031-AL1B-R is announced as NRND/EOL by Qualcomm for new designs. For new designs, choose the pin-compatible AR8033 or AR8035 (which share the QFN-48 footprint but add 100BASE-T1 automotive PHY modes), or migrate to TI DP83867/DP83869 industrial Gigabit PHYs with software-compatible SMI/MII registers. Existing designs should plan for last-time-buy windows.
This page synthesizes distributor pricing, drop-in alternative pin-for-pin cross references, and AR8031 design notes not found in the bare datasheet, including migration paths for EOL NRND devices.
Alternativas directas para AR8031-AL1B-R — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con AR8031-AL1B-R (mismo factor de forma y huella) — difiere en Operating Temperature, Package, MAC Interface, Mounting Type, Cable Diagnostics.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
AR8033-AL1B-R
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
AR8035-AL1B-R
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
AR8031-AL1A-R
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
AR8031-AL1B
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
DP83867CSRGZR
✅ Sustitución directa✓ En stock
$6.45 / unidad
Ver hoja de datos →AR8031-AL1B-R Especificaciones
| Función | 10/100/1000BASE-T Ethernet PHY transceiver |
| Velocidad de datos | 10/100/1000 Mbps |
| MAC Interface | RGMII v2.0, SGMII / 1000BASE-X |
| Supply Voltage (Analog) | 3.15 V to 3.45 V |
| Supply Voltage (Digital I/O) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (VDDIO selectable) |
| Internal LDOs | Integrated 1.2V core LDO and 1.0V VDDIO LDO |
| Receiver Hysteresis | 25 mV |
| Number of Drivers / Receivers | 1 / 1 |
| Duplex | Full |
| Auto-MDI/MDIX | Yes (automatic direction control) |
| IEEE Standards | 802.3, 802.3u, 802.3ab, 802.3az (EEE), 802.1AS / 1588v2 |
| Temperatura de funcionamiento | -40 C to +85 C (industrial grade AL1B) |
| Encapsulado | 48-WFQFN Exposed Pad, 6 x 6 mm |
| Tipo de montaje | Surface Mount (QFN-48-EP) |
| HBM ESD (MDI pins) | 4 kV |
| Cable Reach | 100 m over CAT-5e / CAT-6 UTP |
Configuración de pines de AR8031-AL1B-R
| Pin 1 | TXD0 — RGMII transmit data bit 0 |
| Pin 2 | TXD1 — RGMII transmit data bit 1 |
| Pin 3 | TXD2 — RGMII transmit data bit 2 |
| Pin 4 | TXD3 — RGMII transmit data bit 3 |
| Pin 5 | TX_CTL — RGMII transmit control (TX_EN / TX_ER) |
| Pin 6 | TX_CLK — RGMII transmit clock (125 MHz) |
| Pin 7 | RXD0 — RGMII receive data bit 0 |
| Pin 8 | RXD1 — RGMII receive data bit 1 |
| Pin 9 | RXD2 — RGMII receive data bit 2 |
| Pin 10 | RXD3 — RGMII receive data bit 3 |
| Pin 11 | RX_CTL — RGMII receive control (RX_DV / RX_ER) |
| Pin 12 | RX_CLK — RGMII receive clock (125 MHz recovered) |
| Pin 13 | GTX_CLK — RGMII source-synchronous clock from MAC |
| Pin 14 | MDIO — Management Data I/O (SMI/MIIIM) |
| Pin 15 | MDC — Management Data Clock |
| Pin 16 | INT — Interrupt output (active low) |
| Pin 17 | RESET_N — Hardware reset (active low) |
| Pin 18 | LED0 — Activity/link LED indicator |
| Pin 19 | LED1 — Speed/link LED indicator |
| Pin 20 | LED2 — Activity/link LED indicator |
| Pin 21 | GPIO0 — General-purpose I/O / strap config |
| Pin 22 | GPIO1 — General-purpose I/O / strap config |
| Pin 23 | GPIO2 — General-purpose I/O / strap config |
| Pin 24 | SGMII_SDN — SGMII shutdown control |
| Pin 25 | SGMII_SDP — SGMII data positive |
| Pin 26 | SGMII_SDN_DATA — SGMII data negative |
| Pin 27 | NC — Not connected |
| Pin 28 | AVDD33_A — Analog 3.3V supply A |
| Pin 29 | AVDD33_B — Analog 3.3V supply B |
| Pin 30 | MDI_P0 — Media Dependent Interface pair 0 positive |
| Pin 31 | MDI_N0 — Media Dependent Interface pair 0 negative |
| Pin 32 | MDI_P1 — Media Dependent Interface pair 1 positive |
| Pin 33 | MDI_N1 — Media Dependent Interface pair 1 negative |
| Pin 34 | MDI_P2 — Media Dependent Interface pair 2 positive |
| Pin 35 | MDI_N2 — Media Dependent Interface pair 2 negative |
| Pin 36 | MDI_P3 — Media Dependent Interface pair 3 positive |
| Pin 37 | MDI_N3 — Media Dependent Interface pair 3 negative |
| Pin 38 | AVDD_PLL — Analog 3.3V supply for PLL |
| Pin 39 | XI — 25 MHz crystal input |
| Pin 40 | XO — 25 MHz crystal output |
| Pin 41 | VDDIO — Digital I/O supply (1.5/1.8/2.5/3.3V) |
| Pin 42 | DVDD — Digital core 1.2V (internal LDO output, decouple) |
| Pin 43 | TEST — Factory test pin (tie to GND in production) |
| Pin 44 | NC — Not connected |
| Pin 45 | NC — Not connected |
| Pin 46 | NC — Not connected |
| Pin 47 | NC — Not connected |
| Pin 48 | NC — Not connected |
| Pin EP | EPAD — Exposed thermal pad - tie to GND with multiple vias |
Aplicaciones típicas
AR8031-AL1B-R es adecuado para 6 aplicacións: Industrial Ethernet Switch, Wireless Router / Gateway, IP Camera / Surveillance NVR, 5G Small-Cell Base Station, Industrial IoT Gateway / Edge Box, Printer / MFP Embedded Networking.
Industrial Ethernet Switch
The AR8031-AL1B-R's 1 Gbps RGMII/SGMII MAC interface and -40 C to +85 C industrial temperature rating make it a strong PHY for managed industrial Ethernet switches used on factory floors. Its integrated 25 mV receiver hysteresis rejects common-mode noise from long motor-cable runs, while the integrated 1.2V/1.0V LDOs eliminate two external regulators and shrink the BOM. Each switch port typically uses one AR8031-AL1B-R paired with a discrete RJ-45 + magnetics module, driving 100 m CAT-5e links at line rate. The built-in 1588v2 hardware timestamping enables sub-microsecond PTP synchronization required by EtherCAT, PROFINET IRT, and IEEE 1588 motion-control networks. The 4 kV HBM ESD on MDI pins protects against cable-discharge transients common in unprotected industrial cabinets.
Recomendado
Wireless Router / Gateway
Small-office/home-office Wi-Fi routers and 5G FWA gateways use the AR8031-AL1B-R as the WAN/LAN Ethernet PHY because it integrates the magnetics-termination resistors and runs from a single 3.3V rail. Its RGMII v2.0 interface drops directly into Qualcomm IPQ40xx and IPQ807x SoCs without a glue FPGA, and the SGMII mode is used when routing MAC traffic through an internal 2.5G switch fabric. At 1000BASE-T full-duplex, the AR8031's echo canceller and FFE/DFE/Viterbi equalizer chain keep BER below 10^-10 over 100 m CAT-6 with no external tuning. Auto-MDI/MDIX eliminates the crossover-cable legacy, simplifying user setup. For thermally-constrained plastic enclosures, the 6x6 mm QFN-48 exposed pad dissipates the typical 0.8 W class-A dissipation without a heatsink.
Recomendado
IP Camera / Surveillance NVR
Gigabit IP cameras and NVR recorders benefit from the AR8031-AL1B-R's small 6x6 mm footprint, integrated terminations, and IEEE 802.3az Energy-Efficient Ethernet (EEE) support that drops link power during idle periods. The 1588v2 hardware timestamp on every packet aligns with ONVIF Profile T time-synchronization for forensic-grade timestamping. The 25 mV receiver hysteresis preserves signal integrity when the camera is mounted near fluorescent ballasts or LED PWM drivers that inject common-mode noise on the CAT-5 cable. Each PoE camera uses one AR8031-AL1B-R between the RJ-45/magnetics and the image-processor SoC, supporting 1000BASE-T full-duplex line-rate streaming of H.265 4K video. Industrial temperature qualification enables outdoor cabinet deployment.
Recomendado
5G Small-Cell Base Station
Indoor and outdoor 5G small cells use the AR8031-AL1B-R as the SGMII PHY between the baseband SoC and the backhaul Ethernet switch. The hardware 1588v2 timestamp combined with 802.1AS enables the sub-microsecond phase alignment required for TDD/FR1 and FDD/FR2 air-interface synchronization, which is critical for inter-cell interference coordination and mobility handover. The integrated 1.2V core LDO removes a discrete regulator on the small-cell baseband PCB, and the -40 C to +85 C range supports outdoor pico-cell enclosures. SGMII mode (over 1000BASE-X) routes the backhaul MAC interface over a single LVDS pair to the small-cell baseband, freeing board space for RF components.
Recomendado
Industrial IoT Gateway / Edge Box
Industrial IoT gateways aggregate Modbus TCP, EtherNet/IP, and PROFINET traffic, and the AR8031-AL1B-R serves as the PHY that connects the gateway SoC to the plant-floor switch. Its 1588v2 timestamping enables PTP-based distributed-clock synchronization for time-stamped sensor data, while the integrated terminations reduce the gateway's PCB area to fit into DIN-rail enclosures. According to TI rollover guide SNLA333, the AR8031 family is widely adopted in industrial Linux BSPs (NXP i.MX6/7/8 and Qualcomm IPQ platforms), so Linux drivers are mature. The 25 mV hysteresis and joint-Viterbi equalizer chain ensure robust 1000BASE-T link recovery even on degraded CAT-5e plant cabling.
Recomendado
Printer / MFP Embedded Networking
Office laser printers and multifunction peripherals (MFPs) embed the AR8031-AL1B-R as the gigabit Ethernet PHY on the formatter board, providing AirPrint, Mopria, and IPP-Everywhere compatibility. The integrated switching regulator and LDO shrink the formatter BOM enough to fit alongside the print-engine driver board in the same plastic chassis without EMI issues. Auto-MDI/MDIX allows users to plug either straight-through or crossover cables without failures, and 802.3az EEE reduces idle-state power consumption by approximately 70% to meet ENERGY STAR imaging-equipment criteria. The exposed-pad QFN-48 dissipates the class-A power directly into the printer's metal chassis, eliminating a discrete heatsink.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para AR8031-AL1B-R — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | AR8033-AL1B-R | AR8035-AL1B-R | AR8031-AL1A-R | AR8031-AL1B | DP83867CSRGZR |
|---|---|---|---|---|---|---|
| Package | QFN-48 (6x6 mm) | QFN-48 (6x6 mm) | QFN-48 (6x6 mm) | QFN-48 (6x6 mm) | QFN-48 (6x6 mm) | QFN-48 (7x7 mm) |
| Brand | Qualcomm | Qualcomm | Qualcomm | Qualcomm | Qualcomm | Texas Instruments |
| Max Data Rate | 1000 Mbps | 1000 Mbps | 1000 Mbps + 1000BASE-T1 | 1000 Mbps | 1000 Mbps | 1000 Mbps |
| MAC Interface | RGMII + SGMII | RGMII + SGMII | RGMII + SGMII + 1000BASE-T1 | RGMII + SGMII | RGMII + SGMII | RGMII + SGMII |
| Supply Voltage | 3.15 V to 3.45 V | 3.15 V to 3.45 V | 3.15 V to 3.45 V | 3.15 V to 3.45 V | 3.15 V to 3.45 V | 2.5 V / 3.3 V |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | 0 C to +70 C | -40 C to +85 C | -40 C to +85 C |
| 1588v2 Hardware Timestamping | Yes | Yes | Yes | Yes | Yes | Optional (DP83867E variant) |
| Receiver Hysteresis | 25 mV | 25 mV | 25 mV | 25 mV | 25 mV | 30 mV |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | Active |
Diferenciadores clave
- Industrial temperature rating at 1G speed (frente a AR8031-AL1A-R)
- Cross-vendor migration path with software compatibility (frente a DP83867CSRGZR)
- Same silicon, tape-and-reel shipping media (frente a AR8031-AL1B)
Notas de diseño
The AR8031-AL1B-R requires a single 3.3V analog supply on AVDD33 (3.15 V to 3.45 V) and an independent VDDIO rail (1.5/1.8/2.5/3.3 V) for the RGMII/SGMII MAC interface. Both rails must be decoupled with 1 uF + 0.1 uF + 10 nF X7R ceramic capacitors placed within 2 mm of the supply pins; the 0.1 uF cap is critical for high-frequency noise rejection on the PLL supply (AVDD_PLL). Estimated: total quiescent power is approximately 0.6 W at 1000BASE-T full-duplex with both internal LDOs active, rising to approximately 0.8 W during autoneg training.
The QFN-48 6x6 mm package relies on the exposed thermal pad for heat dissipation. Solder the EPAD to a 10 mm x 10 mm copper pour with at least 9 thermal vias (0.3 mm drill, 1 mm pitch) to the inner ground plane. Estimated: theta_JA on a JEDEC JESD51 4-layer board is approximately 28 C/W; at 0.8 W class-A dissipation, junction-to-ambient temperature rise is approximately 22 C above ambient, leaving comfortable margin to the 125 C junction limit. Do not place any signal traces under the EPAD keepout region.
Route the MDI differential pairs (MDI_P/N[3:0]) as 100 ohm differential with intra-pair length matching below 0.5 mm, and route them on the top layer with a continuous ground reference plane underneath. Keep the 25 MHz crystal traces (XI/XO) shorter than 5 mm and shield them with a ground guard ring; place load capacitors (per datasheet crystal table) within 2 mm of the XI/XO pins. Per TI rollover guide SNLA333, the MDIO pull-up resistor is on pin 41 of the AR8031 but pin 17 of the DP83867 - swap this single resistor (2.2 kOhm to VDDIO) if migrating designs.
Do not strap MDIO or RESET_N signals through long traces - place 4.7 kOhm pull-ups on each, per the datasheet SMI timing section. According to Qualcomm's errata, AR8031 revisions below silicon rev A0 may exhibit SGMII link-up failure when the MAC PHY clock is sourced from a TCXO rather than the on-chip oscillator; use a quartz crystal for XI/XO and avoid TCXO fanout into the PHY. When migrating to TI DP83867, verify the SMI register map - bits differ for EEE advertisement, link-quality diagnostics, and strap configuration - and re-run the PHY firmware initialization sequence.
Información de cumplimiento
RoHS and REACH compliant per LCSC and JLCPCB product detail pages. The AR8031-AL1B-R is not AEC-Q100 qualified - for AEC-Q100 automotive Ethernet, use AR8033/AR8035 variants with automotive qualification or TI DP83867-Q1.
