CD4026BE - CMOS Decade Counter with 7-Segment Outputs | TI
N.º de pieza: CD4026BE ✓ ActivoCD4026BE Descripción general
A CMOS decade counter is a digital logic device that counts clock pulses through ten states and divides a clock frequency by ten. The CD4026B belongs to the broader CMOS counter, divider, display-driver, and logic-IC hierarchy. Its decoded 7-segment outputs are designed for one display digit, making it useful for instrument panels, counters, timers, clock displays, and low-power numerical indicators. Texas Instruments identifies the device as particularly advantageous where low power dissipation and a low package count are important.
The CD4026BE combines a 5-stage Johnson decade counter with an output decoder. Common control inputs include CLOCK, RESET, and INHIBIT, while decoded segment outputs drive the display elements. A display-enable output provides control over the decoded outputs. This integration allows a designer to replace a separate counter, decoder, and display-control interface with one dedicated IC, reducing component count and simplifying PCB layout.
The device operates across a wide 3 V to 18 V supply range, allowing use in both low-voltage and higher-voltage CMOS systems. Its static counter operation supports DC through 6 MHz typical at Vpp = 10 V, making it appropriate for low-frequency timing and counting as well as higher-speed pulse-counting functions. The CMOS implementation supports low-power logic operation, although actual power consumption depends on supply voltage, clock activity, and the display load connected to the segment outputs.
Typical applications include digital frequency meters, event counters, decade dividers, appliance timers, industrial panel displays, laboratory counters, and sequential display indicators. The decoded outputs are appropriate for common-cathode or common-anode seven-segment arrangements when the output polarity and segment interface are handled correctly. The display-enable function is particularly useful for blanking a display during reset, test, or controlled operating intervals.
Designers should verify the segment polarity, clock-edge behavior, reset behavior, and inhibit function against the manufacturer's pin-description table before connecting a display. The input must not exceed the device's specified 18 V maximum supply voltage, and unused inputs should be held at a defined logic level rather than left floating. Decoupling capacitors should be placed close to the supply pins, while display-routing traces should be kept away from sensitive clock and reset nodes.
This page consolidates the device's operating characteristics, package details, drop-in alternatives, application guidance, and practical implementation notes. It supports faster component selection while keeping the key design checks centered on supply limits, counter timing, display polarity, and exact 16-pin footprint compatibility.
Alternativas directas para CD4026BE — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con CD4026BE (mismo factor de forma y huella) — difiere en Counter Architecture, Mounting Type.
CD4026BM
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
CD4026BF
✅ Sustitución directa ⚠️ Especificaciones sin verificarConsulte el precio
Ver hoja de datos →HEF4026BP
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
HCF4026BE
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
MC14026BN
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
CD4026BE Valores máximos y características eléctricas
| Product Type | CMOS decade counter/divider with decoded 7-segment outputs |
| Counter Architecture | 5-stage Johnson decade counter |
| Decoded Output | 7-segment display output |
| Supply Voltage Range | 3 V to 18 V |
| Frecuencia de reloj máxima | 16 MHz |
| Fully Static Counter Frequency | DC to 6 MHz typical at Vpp = 10 V |
| Counter Width | 5 bit |
| Counting Direction | Positive edge |
| Display Elements per Package | 1 element |
| Common Control Inputs | CLOCK, RESET, and INHIBIT |
| Display Enable | Yes |
| Encapsulado | 16-PDIP |
| Recuento de pines | 16 pins |
| Tipo de montaje | Through-hole dual-in-line |
| Technology | CMOS |
Guía de configuración de pines de CD4026BE 16-pdip
Configuración de pines para CD4026BE (encapsulado 16-pdip). Este CI digital incluye GPIO, interfaces de comunicación (UART, SPI, I2C) y pines de alimentación. Consulte la hoja de datos del fabricante para conocer las funciones alternativas de los pines y las opciones de configuración. Esencial para el diseño de sistemas embebidos y el diseño de PCB.
No hay datos detallados de patillaje disponibles para CD4026BE.
Consulte la hoja de datos para ver la configuración completa de patillas.
Aplicaciones típicas
CD4026BE es adecuado para 6 aplicacións: Digital Frequency Counter, Single-Digit Event Counter, Appliance and Equipment Timer, Industrial Status Panel, Timing and Divider Circuit, Educational Counter and Display Trainer.
Digital Frequency Counter
The CD4026BE suits compact digital frequency counters because its 5-stage Johnson decade counter and integrated 7-segment decoder reduce the number of separate counter and decoding ICs. A pulse train can be applied to CLOCK while RESET establishes the starting state and INHIBIT provides run or hold control. The 16-PDIP package is convenient for through-hole instruments and educational equipment. Because the device is specified for fully static counting from DC to 6 MHz typical at Vpp = 10 V, designers should verify the intended input frequency and signal levels against the manufacturer timing curves before finalizing the front end.
Recomendado
Single-Digit Event Counter
A CD4026BE can form the central counting and display element of a single-digit event counter for panels, laboratory apparatus, and educational panels. Each clock pulse advances the internal decade state, and the decoded outputs directly represent one decimal digit. RESET can clear the count, while INHIBIT can hold or inhibit counting depending on the required control logic. The integrated display-enable output simplifies blanking during reset or test. With a 3 V to 18 V operating range and low-power CMOS characteristics, the device is well suited to compact counters where separate decoder logic would add board area and component count.
Recomendado
Appliance and Equipment Timer
The CD4026BE is useful in appliance timers, industrial interval counters, and equipment-control panels that need a visible decimal count. Its decade-counter architecture provides ten states, making it appropriate for counting units, cycles, or completed events rather than unrestricted binary values. The CLOCK, RESET, and INHIBIT inputs support the primary control functions needed by a timer, and decoded segment outputs reduce the external circuitry required to present elapsed units. The 16-PDIP package also favors through-hole construction and repairable industrial equipment. Ensure the display current remains within the output ratings and that any relay or load-driving stage is isolated from the counter outputs.
Recomendado
Industrial Status Panel
The CD4026BE fits industrial status panels that display one decimal process value, such as cycle count, batch count, or step number. Its integrated 7-segment decoder converts the internal Johnson-counter state into display-ready segment signals, while the display-enable output allows the panel to blank inactive digits or hide a transient count during reset. The 3 V to 18 V supply range supports integration with conventional CMOS logic levels. For long wiring runs or noisy industrial environments, use suitable drivers and protection networks, and route the clock and reset lines away from motor and switching-control traces.
Recomendado
Timing and Divider Circuit
The CD4026BE can divide a periodic input by ten when the output state is used as a clock for downstream logic. Its fully static operation from DC through 6 MHz typical at Vpp = 10 V makes it applicable to low-frequency timing, periodic sequencing, and pulse-rate reduction. The on-chip decoder does not have to be used if only the counter state is required, allowing the same package to serve as a dedicated divider in cost-sensitive designs. Keep the clock waveform within the manufacturer's input-level and transition-time limits, and use Schmitt-level conditioning where a noisy source could produce multiple transitions during a slow clock edge.
Recomendado
Educational Counter and Display Trainer
The CD4026BE is appropriate for electronics trainers that demonstrate counting, decoding, display blanking, and logic-control concepts on a breadboard or through-hole teaching board. Its clear division between CLOCK, RESET, INHIBIT, and decoded segment outputs makes internal behavior easy to observe with seven-segment indicators. The 16-PDIP format exposes every connection for probing, while the integrated decoder shows how a Johnson counter becomes a usable decimal display. Use a current-limited display arrangement and defined logic levels on unused control inputs. The low-power CMOS implementation also keeps classroom power consumption manageable when the input clock frequency is low.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para CD4026BE — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | CD4026BM | CD4026BF | HEF4026BP | HCF4026BE | MC14026BN |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | NXP | STMicroelectronics | onsemi |
| Package | 16-PDIP | 16-PDIP | 16-PDIP | 16-PDIP | 16-PDIP | 16-PDIP |
| Product Type | CMOS decade counter/divider with decoded 7-segment outputs | CD4026B family counter/decoder | CD4026B family counter/decoder | CMOS decade counter/decoder | CMOS decade counter/decoder | CMOS decade counter/decoder |
| Supply Voltage Range | 3 V to 18 V | 3 V to 18 V class | 3 V to 18 V class | 3 V to 18 V class | 3 V to 18 V class | 3 V to 18 V class |
| Counter Architecture | 5-stage Johnson decade counter | 5-stage Johnson decade counter | 5-stage Johnson decade counter | Equivalent CMOS decade-counter architecture | Equivalent CMOS decade-counter architecture | Equivalent CMOS decade-counter architecture |
| Display Output | Decoded 7-segment output for 1 element | Decoded 7-segment output | Decoded 7-segment output | Decoded 7-segment output | Decoded 7-segment output | Decoded 7-segment output |
| Control Inputs | CLOCK, RESET, and INHIBIT | CLOCK, RESET, and INHIBIT | CLOCK, RESET, and INHIBIT | Equivalent counter-control interface | Equivalent counter-control interface | Equivalent counter-control interface |
Diferenciadores clave
- Combines decade counting and one-digit seven-segment decoding (frente a CD4024BE)
- Distinguished from the CD4033BE by display-control features (frente a CD4033BE)
- Wide CMOS supply range for embedded numerical displays (frente a HCF4026BE)
Notas de diseño
Do not assume every CD4026-family ordering code has identical display polarity or temperature grading. Before replacing CD4026BE, compare the CLOCK edge, RESET behavior, INHIBIT truth table, decoded segment states, display-enable polarity, electrical timing, and operating-temperature limits. A physical 16-pin outline match is necessary but not sufficient for a functional drop-in decision. Update the schematic and verify the display in every digit state after substitution.
Route the CLOCK and RESET nets away from display outputs and switching-control traces to reduce false clocking. Place the supply bypass capacitor close to the device's supply and ground pins, and keep the return path short. When driving external displays through long cables or high-current displays, use suitable buffer or driver stages rather than increasing the load on the counter outputs. Confirm the selected display's common-anode or common-cathode configuration and segment polarity before final PCB routing.
The CD4026BE requires clean, monotonic transitions at CLOCK, RESET, and INHIBIT. At low supply voltage or with slow input edges, use a suitable Schmitt-trigger conditioning stage or revise the source to meet the manufacturer's transition-time requirement. A noisy clock can produce extra counts that are difficult to diagnose in a display system. Keep the counting source away from inductive loads and provide a defined reset state during power-up if the displayed count must not contain stale values.
Información de cumplimiento
The CD4026BE is a CMOS logic IC rather than an automotive-qualified device. Specific RoHS, REACH, lead-free, halogen-free, and conflict-minerals declarations were not identified in the cited manufacturer and distributor records.