CDK1307DILP40 - 13-bit 80MSPS 60mW Ultra-Low Power ADC | MaxLinear
N.º de pieza: CDK1307DILP40 ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.85 | $1.385,00 |
| 500 | $11.4 | $5.700,00 |
| 1.000 | $9.6 | $9.600,00 |
CDK1307DILP40 Descripción general
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous-time, continuous-amplitude analog signals into discrete-time, discrete-amplitude digital codes. The CDK1307 family belongs to the pipeline ADC category, which uses a multi-stage switched-capacitor architecture to deliver high sample rates at moderate resolution. Within the broader IC hierarchy, an ADC sits under data converters, which themselves are a sub-category of data acquisition ICs and ultimately signal conditioning semiconductors used in virtually every electronic system that bridges the analog physical world with digital processors.
Key features highlighted in the verified data include a 72.4 dB SNR at an analog input frequency of 8 MHz, internal reference circuitry that eliminates the need for an external voltage reference, a 1.8 V core supply voltage, and a wide 1.7 V to 3.6 V I/O supply range that interfaces directly to 1.8 V, 2.5 V, and 3.3 V logic. The differential clock interface is optimized for low jitter, and a highly linear track-and-hold amplifier (THA) preserves dynamic performance at input frequencies up to the Nyquist limit. Two idle modes - Standby and Power Down - provide fast wake-up with minimized quiescent energy, which is critical for battery-powered or duty-cycled systems.
The pipeline architecture uses successive low-resolution stages with digital error correction, achieving 13-bit linearity without laser trimming. Parallel CMOS outputs simplify the digital interface to FPGAs, ASICs, or microcontrollers without requiring an external serializer. The combination of high SNR, low power dissipation, and a small 40-pin QFN footprint makes the CDK1307DILP40 suitable for portable instrumentation where every milliwatt and every square millimeter matter.
Typical applications include medical imaging front ends, portable test equipment, digital oscilloscopes, IF-sampling communications receivers, and handheld industrial sensors. The wide I/O voltage range also simplifies interfacing to modern low-voltage FPGAs without level shifters.
When designing with this part, ensure the analog input network presents a differential drive to achieve the rated 72.4 dB SNR. Decouple the 1.8 V analog supply and the I/O supply separately near the IC pins, and provide a clean low-jitter clock through the differential CLK+/CLK- pins to maximize spurious-free dynamic range.
This page consolidates distributor pricing, parametric data, and drop-in-compatible alternatives for the CDK1307DILP40, providing practical engineering context beyond the raw manufacturer datasheet.
Alternativas directas para CDK1307DILP40 — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con CDK1307DILP40 (mismo factor de forma y huella) — difiere en Resolution, Package, Reference, Architecture, Manufacturer.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
CDK1307CILP40
✅ Sustitución directa✓ En stock
$3.95 / unidad
Ver hoja de datos →CDK1307BILP40
✅ Sustitución directa✓ En stock
$3.22 / unidad
Ver hoja de datos →CDK1307AILP40
✅ Sustitución directa✓ En stock
$5.21 / unidad
Ver hoja de datos →CDK1308AILP40
✅ Sustitución directa✓ En stock
$4.1 / unidad
Ver hoja de datos →CDK1307DILP40 Valores máximos y características eléctricas
| Resolución | 13 bit |
| Sampling Rate (max) | 80 MSPS |
| Power Dissipation (typ) | 60 mW at 80 MSPS |
| Family Power Grades | 17 / 19 / 33 / 50 / 60 / 75 mW across speed grades |
| SNR | 72.4 dB at Fin = 8 MHz |
| Analog Supply Voltage | 1.8 V (core) |
| I/O Supply Voltage | 1.7 V to 3.6 V |
| Output Interface | Parallel CMOS |
| Reference | Internal reference circuitry |
| Clock Input | Differential, low-jitter |
| Track-and-Hold | Highly linear, optimized to Nyquist |
| Idle Modes | Standby and Power Down |
| Encapsulado | 40-pin QFN |
| Pin Compatibility | Pin-compatible with CDK1308 |
| Pin Compatibility (family) | Same 40-pin QFN for A/B/C/D speed grades |
Guía de configuración de pines de CDK1307DILP40 40-pin qfn
Configuración de pines para CDK1307DILP40 (encapsulado 40-pin qfn). Este componente analógico presenta pines de entrada, salida y alimentación. Consulte la hoja de datos del fabricante para conocer las configuraciones de los pines de ajuste de offset, compensación y habilitación. Ideal para circuitos de acondicionamiento de señal y amplificadores.
No hay datos detallados de patillaje disponibles para CDK1307DILP40.
Consulte la hoja de datos para ver la configuración completa de patillas.
Aplicaciones típicas
CDK1307DILP40 es adecuado para 6 aplicacións: Medical Imaging Front End, Portable Test Equipment, Digital Oscilloscope Channels, IF-Sampling Communications Receivers, Handheld Industrial Sensors, Low-Power FPGA Data Acquisition.
Medical Imaging Front End
The CDK1307DILP40 suits medical imaging front ends that demand wide dynamic range at low power. Its 13-bit resolution and 72.4 dB SNR at 8 MHz input support ultrasound beamformers and portable patient monitors where transducer signals are digitized at IF. The 60 mW dissipation at 80 MSPS keeps battery-powered cart-based ultrasound systems within thermal budgets, while the internal reference eliminates external precision components that would otherwise bloat the BOM. The 1.7-3.6 V I/O range lets the parallel CMOS outputs interface directly to a low-voltage FPGA without level translation, shrinking board area.
Recomendado
Portable Test Equipment
Handheld oscilloscopes and portable spectrum analyzers benefit from the CDK1307DILP40's ultra-low 60 mW dissipation at 80 MSPS. Battery run-time is dominated by the ADC's mW-per-MSPS ratio, and this part is among the lowest in its class. The internal reference removes the need for a precision external reference, and the differential low-jitter clock input preserves SNR at IF frequencies. Two idle modes - Standby and Power Down - let the duty-cycled instrument sip quiescent current between captures, extending field deployment time on a single battery charge.
Recomendado
Digital Oscilloscope Channels
The CDK1307DILP40's 80 MSPS sample rate and 13-bit resolution fit mainstream digital oscilloscope channels up to ~30 MHz analog bandwidth. The parallel CMOS output streams 13-bit words directly into an FPGA-based acquisition memory at full bus width, avoiding the latency of a serialized LVDS interface. The 1.8 V core plus 1.7-3.6 V I/O supplies let the ADC and a modern Xilinx or Lattice FPGA share the same 1.8 V rail, simplifying power architecture. Designers can populate the same QFN-40 footprint with the CDK1308 for higher-bit-count channels on premium scopes.
Recomendado
IF-Sampling Communications Receivers
Software-defined radio and IF-sampling communications receivers digitize down-converted IF signals at tens of MHz. The CDK1307DILP40's 72.4 dB SNR at 8 MHz input and Nyquist-optimized track-and-hold amplifier preserve signal integrity in this band, while the 80 MSPS ceiling supports IFs up to ~40 MHz before aliasing becomes an issue. The differential clock input rejects common-mode noise from the local oscillator chain, critical for maintaining spurious-free dynamic range. Combined with 60 mW dissipation, the part enables multi-channel diversity receivers in compact SDR chassis.
Recomendado
Handheld Industrial Sensors
Battery-powered vibration analyzers, acoustic emission sensors, and portable gas chromatographs all benefit from the CDK1307DILP40's 60 mW dissipation and internal reference. Industrial sensor front ends often digitize transducer outputs at IF, where 13-bit resolution and 72.4 dB SNR suffice for vibration spectrum analysis. The Standby and Power Down modes let a duty-cycled sensor wake only when triggered, extending months-long battery life in remote installations. The wide 1.7-3.6 V I/O range simplifies interfacing to industrial 3.3 V MCUs without level shifters.
Recomendado
Low-Power FPGA Data Acquisition
FPGA-based data acquisition cards in industrial, scientific, and medical systems use the CDK1307DILP40 as a low-power front-end ADC. The parallel CMOS outputs map cleanly into FPGA LVCMOS receivers without serializers or deserializers, simplifying the FPGA firmware. The 1.8 V analog core and 1.7-3.6 V digital I/O supply enable single-rail designs when paired with a modern Lattice ECP5 or Xilinx Artix-7 FPGA on a 1.8 V HP bank. The QFN-40 footprint keeps the analog front end compact, leaving board area for additional channels or DSP resources.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para CDK1307DILP40 — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | CDK1307CILP40 | CDK1307BILP40 | CDK1307AILP40 | CDK1308AILP40 | ADS8401IPFBT |
|---|---|---|---|---|---|---|
| Package | 40-pin QFN | 40-pin QFN (same) | 40-pin QFN (same) | 40-pin QFN (same) | 40-pin QFN (same) | TQFP-48 (different) |
| Brand | MaxLinear (formerly Cadeka) | MaxLinear | MaxLinear | MaxLinear | MaxLinear | Texas Instruments |
| Resolution | 13 bit | 13 bit | 13 bit | 13 bit | Higher than 13-bit | 16 bit |
| Maximum Sample Rate | 80 MSPS | 65 MSPS (-19%) | 40 MSPS (-50%) | 20 MSPS (-75%) | Same family speed grades | 1 MSPS (SAR, not pipeline) |
| Output Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
Diferenciadores clave
- Lowest power dissipation at 80 MSPS in its pin-compatible family (frente a CDK1307DILP40 vs CDK1308 at 80 MSPS)
- Pin-compatible across the CDK1307 family and the CDK1308 (frente a CDK1307DILP40 vs discrete ADC alternatives)
- Wide 1.7-3.6 V I/O supply eliminates level shifters (frente a CDK1307DILP40 vs fixed-voltage-output ADCs)
- Internal reference removes external precision components (frente a CDK1307DILP40 vs external-reference ADCs)
Notas de diseño
Decouple the 1.8 V analog core supply and the 1.7-3.6 V I/O supply with separate local regulators or at least separate ferrite beads from a common rail. Place a 10 uF bulk plus 0.1 uF ceramic decoupling pair as close as possible to each supply pin on the 40-pin QFN. The CDK1307 family datasheet specifies the two supplies must be brought up cleanly with monotonic edges to avoid digital error correction glitches on first power-up. Estimated: total quiescent current draw is roughly 33 mA (60 mW / 1.8 V) at 80 MSPS with CMOS output loads.
The 40-pin QFN has an exposed thermal pad that must be soldered to a continuous ground plane for both thermal dissipation and low-inductance ground return. Use a via array (at least 4x4 vias on 1.0 mm pitch) directly under the EP to stitch the top-side ground pour to inner ground planes. Keep the analog input traces differential and length-matched to within 0.5 mm to preserve the rated 72.4 dB SNR at 8 MHz input.
Drive the differential clock inputs (CLK+/CLK-) with a low-jitter source such as a dedicated clock generator or a PLL output, never with a digital GPIO directly. Jitter on the clock translates directly into aperture uncertainty and degrades SNR. If using a transformer-coupled clock from a sine oscillator, place the transformer within 5 mm of the clock pins and keep the clock traces over a continuous ground plane to avoid coupling noise into the analog inputs.
Do not exceed the absolute maximum analog input range or the part will latch up. Ensure the common-mode voltage of the differential analog inputs is within the input common-mode range specified in the datasheet. Avoid routing digital CMOS output traces directly under the analog input network on inner layers; route them on the opposite side of the ground plane to minimize digital noise coupling into the analog front end.
When migrating between CDK1307 family speed grades (A/B/C/D suffix) or to the higher-resolution CDK1308, verify that the standby and power-down pin logic levels match your FPGA/MCU GPIO output - all family members use the same pinout, but timing diagrams differ slightly between grades. Always re-validate the ADC's pipeline latency in your FPGA capture firmware if you switch from 80 MSPS to a slower grade, because latency scales inversely with sample rate in pipeline ADCs.
Información de cumplimiento
RoHS and lead-free per Cadeka/MaxLinear product page; AEC-Q100 automotive qualification not stated - this is an industrial/consumer grade ADC. Halogen-free status not explicitly confirmed in the verified web data.
