CS5581-ISZ - 16-bit 200kSps Sigma-Delta ADC | Cirrus Logic
N.º de pieza: CS5581-ISZ ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.85 | $1.385,00 |
| 500 | $11.4 | $5.700,00 |
| 1.000 | $9.75 | $9.750,00 |
CS5581-ISZ Descripción general
What is a sigma-delta ADC? A sigma-delta (ΔΣ) analog-to-digital converter is a type of data converter that uses oversampling and noise shaping to achieve high resolution at moderate bandwidth. Unlike successive-approximation registers (SAR) or flash converters, sigma-delta ADCs trade absolute sample rate for very high in-band signal-to-noise ratio, making them ideal for precision measurement, instrumentation, and audio applications. The CS5581 belongs to the data acquisition IC category, which sits hierarchically within mixed-signal ICs, integrated circuits, and ultimately semiconductors.
Key features include a single-ended analog input with integrated input buffers that eliminate the need for external op-amp buffers, a 5 µs conversion time that settles in a single conversion cycle, and a serial interface suitable for connection to microcontrollers, DSPs, or FPGAs. The 24-SSOP package offers a compact footprint for multi-channel data acquisition boards. The device targets high-throughput 16-bit measurements where signal integrity and noise rejection outweigh raw sample rate.
From an architectural perspective, the CS5581 combines a switched-capacitor modulator with a digital decimation filter, enabling true 16-bit resolution with no missing codes. The high input-impedance on-chip buffer reduces source-impedance-induced gain errors and lets the ADC drive directly from sensor bridges, thermocouples, or instrumentation front ends without precision external buffering.
Typical applications include industrial process control, precision weigh scales, multi-channel data acquisition systems, medical instrumentation front ends, and audio bandwidth measurement where its 80 dB SNR and low integral nonlinearity deliver accurate digitisation of low-level analog signals. A primary use case is replacing legacy 16-bit SAR ADCs in measurement instruments where higher noise rejection is required.
When designing with the CS5581, observe the supply decoupling guidance: place 0.1 µF ceramic capacitors close to each analog supply pin and add bulk electrolytic capacitors to suppress switching supply noise. Ensure the analog input common-mode voltage sits within the specified range and that the digital interface lines are length-matched and series-terminated near the host controller to avoid reflections.
This page synthesises distributor pricing from DigiKey/Mouser, drop-in alternative MPNs from the same Cirrus Logic family, and practical PCB layout notes that complement the manufacturer datasheet and accelerate design-in decisions.
Alternativas directas para CS5581-ISZ — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con CS5581-ISZ (mismo factor de forma y huella) — difiere en Converter Type, Resolution, Number of Channels, Package, Architecture.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
CS5581
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
CS5580
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
CS5582
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
AD7730BRUZ
✅ Sustitución directa✓ En stock
$13.1 / unidad
Ver hoja de datos →ADS131A04
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
CS5581-ISZ Valores máximos y características eléctricas
| Resolución | 16 bit |
| Sample Rate | 200 kSps |
| Number of Channels | 1 |
| Converter Type | Sigma-Delta (ΔΣ) |
| Analog Supply Voltage | ±2.5 V or 5 V |
| Analog Input Type | Single-ended |
| On-chip Input Buffer | Yes (high input impedance) |
| Conversion Time | 5 µs |
| Settling Behavior | Settles in one conversion |
| Linearity Error | 0.0008% (≈0.5 LSB) |
| Signal-to-Noise Ratio (SNR) | 80 dB |
| Differential Non-Linearity (DNL) | ±0.1 LSB max |
| Encapsulado | 24-SSOP |
| Tipo de montaje | Surface Mount |
Configuración de pines de CS5581-ISZ
| Pin 1 | AVDD — Analog positive supply |
| Pin 2 | AVSS — Analog negative supply |
| Pin 3 | VREF — Reference voltage input |
| Pin 4 | AIN+ — Analog input positive (single-ended) |
| Pin 5 | AIN- — Analog input negative |
| Pin 6 | BUF_OUT — Buffered analog output (test) |
| Pin 7 | GND — Analog ground |
| Pin 8 | NC — Not connected |
| Pin 9 | NC — Not connected |
| Pin 10 | NC — Not connected |
| Pin 11 | DVDD — Digital supply |
| Pin 12 | DGND — Digital ground |
| Pin 13 | SCLK — Serial clock input |
| Pin 14 | SDOUT — Serial data output |
| Pin 15 | SYNC — Synchronisation / chip select |
| Pin 16 | CONVST — Conversion start input |
| Pin 17 | DRDY — Data ready output |
| Pin 18 | RST — Reset input |
| Pin 19 | TEST1 — Test pin (factory use) |
| Pin 20 | TEST2 — Test pin (factory use) |
| Pin 21 | NC — Not connected |
| Pin 22 | NC — Not connected |
| Pin 23 | NC — Not connected |
| Pin 24 | NC — Not connected |
Aplicaciones típicas
CS5581-ISZ es adecuado para 7 aplicacións: Industrial Weigh Scales and Load Cells, Precision Data Acquisition Systems, Medical Instrumentation Front Ends, Process Control and Industrial Sensors, Audio Bandwidth Measurement Equipment, Sensor Signal Conditioning Modules, Power Metering and Energy Monitoring.
Industrial Weigh Scales and Load Cells
The CS5581-ISZ's integrated high-impedance input buffer drives directly from strain-gauge bridge sensors without external op-amp buffering, eliminating 2-4 active components per channel. Its 0.0008% linearity error (~0.5 LSB) and 80 dB SNR deliver accurate load readings across 0.1% to 1% FS measurement accuracy. Sigma-delta noise shaping rejects 50/60 Hz mains interference critical for industrial scales in factory environments, while the 24-SSOP footprint supports compact multi-channel PCB layouts where multiple CS5581-ISZ parts interface to a host MCU via serial interface.
Recomendado
Precision Data Acquisition Systems
In multi-channel data acquisition boards, the CS5581-ISZ provides 16-bit resolution at 200 kSps per channel with sigma-delta noise shaping that delivers superior in-band SNR compared to SAR ADCs. The integrated input buffer accepts signals from sensors with source impedances up to several kΩ without degrading linearity, and the 5 µs single-conversion settling removes the latency penalty typical of multi-cycle sigma-delta ADCs. For DAQ systems requiring per-channel synchronisation, multiple CS5581-ISZ parts share a common serial SCLK line to the host controller.
Recomendado
Medical Instrumentation Front Ends
The CS5581-ISZ serves medical instrumentation front ends (ECG, EEG, blood-pressure monitors) where its 80 dB SNR captures low-amplitude bioelectric signals with adequate dynamic range. Sigma-delta noise shaping rejects electromagnetic interference from medical equipment without aggressive analog filtering, while the integrated high-impedance input buffer presents minimal load to high-impedance electrodes. The 24-SSOP package enables compact patient-monitoring PCB layouts where board area is at a premium and multiple CS5581-ISZ parts digitise parallel bioelectric channels.
Recomendado
Process Control and Industrial Sensors
Industrial process control loops demand 16-bit absolute accuracy at moderate bandwidth to digitise 4-20 mA, 0-10 V, and thermocouple/millivolt sensor signals. The CS5581-ISZ's 0.0008% linearity and ±0.1 LSB DNL preserve control-loop accuracy across the full input range, while its sigma-delta architecture rejects switching power supply noise common in industrial enclosures. Single-conversion settling at 5 µs supports loop update rates above 100 kHz for high-speed valve and actuator control systems.
Recomendado
Audio Bandwidth Measurement Equipment
Audio test and measurement equipment digitises analog signals from 20 Hz to 20 kHz with 80 dB dynamic range. The CS5581-ISZ's 80 dB SNR covers 16-bit audio with adequate headroom, while sigma-delta noise shaping inherently rejects out-of-band noise without additional anti-aliasing filters. The 200 kSps throughput supports oversampling at 5x the audio Nyquist rate for clean, alias-free audio capture in test instruments, and the integrated input buffer accepts signals directly from microphone preamps.
Recomendado
Sensor Signal Conditioning Modules
Generic sensor signal conditioning modules use the CS5581-ISZ to digitise outputs from pressure transducers, flow meters, and chemical sensors with 16-bit accuracy. The integrated input buffer directly accepts high-impedance sensor outputs, eliminating external op-amp buffers that add cost, noise, and drift. At 200 kSps, the CS5581-ISZ supports control loops and data logging where transient response matters, and the 24-SSOP package fits small form-factor transducer modules where PCB area is constrained.
Recomendado
Power Metering and Energy Monitoring
Power metering ICs require 16-bit sigma-delta ADCs to measure current and voltage waveforms at 4 kHz bandwidth with sufficient dynamic range for harmonic analysis. The CS5581-ISZ's 80 dB SNR and integrated input buffer suit single-phase power-meter designs where two CS5581-ISZ parts digitise voltage and current channels simultaneously. The 24-SSOP package is industry-standard for energy-meter PCBs, and the serial interface connects directly to metrology MCUs without glue logic.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para CS5581-ISZ — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | CS5581 | CS5580 | CS5582 | AD7730 | ADS131A04 |
|---|---|---|---|---|---|---|
| Brand | Cirrus Logic | Cirrus Logic | Cirrus Logic | Cirrus Logic | Analog Devices | Texas Instruments |
| Package | 24-SSOP | 24-SSOP (same) | 24-SSOP (same) | 24-SSOP (same) | 24-SSOP (same) | 24-SSOP (same) |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 24 bit | 24 bit |
| Sample Rate | 200 kSps | 200 kSps | ~180 kSps (within 10%) | ~160 kSps (within 20%) | ~180 kSps (within 10%) | 32 kSps (lower) |
| Architecture | Sigma-Delta | Sigma-Delta | Sigma-Delta | Sigma-Delta | Sigma-Delta | Sigma-Delta |
| Channels | 1 | 1 | 1 | 2 (within 20%) | 1 | 4 |
| Input Buffer | Integrated (high-Z) | Integrated | Integrated | Integrated | Integrated | Integrated |
| SNR | 80 dB | 80 dB | 80 dB | 80 dB | ~90 dB (higher) | ~100 dB (higher) |
Diferenciadores clave
- On-chip high-impedance input buffer eliminates external op-amp (frente a ADS8381IBPFBR)
- Single-conversion settling at 5 µs eliminates pipeline latency (frente a ADS8505IDBRG4)
- Sigma-delta noise shaping inherently rejects mains interference (frente a ADS8401IBPFBT)
- Compact 24-SSOP package with industrial footprint (frente a AD9268XCPZ-125)
Notas de diseño
Decouple AVDD and DVDD with a 0.1 µF ceramic capacitor placed within 5 mm of each supply pin. Add a 10 µF bulk electrolytic or tantalum capacitor to suppress switching supply noise. For ±2.5 V operation, ground AVSS or wire it to a clean negative rail. Star-ground the analog and digital ground returns at the ADC GND pin to avoid digital switching currents flowing through the analog ground plane. Estimated: assuming 200 kSps output rate and 5 V supply, the CS5581-ISZ draws approximately 30-40 mA from AVDD based on the 16-bit sigma-delta topology; verify against the manufacturer datasheet before finalising power budget.
Route analog input traces as short, guarded differential pairs to the AIN+ and AIN- pins. Keep digital interface lines (SCLK, SDOUT, SYNC, CONVST, DRDY) away from the analog input traces and surround them with a ground pour on the same layer. Use a 4-layer PCB with continuous ground and power planes to provide shielding for the analog input buffer; place the CS5581-ISZ over the analog ground plane, not split planes.
Series-terminate the SCLK, SDOUT, SYNC, and DRDY lines with 33 Ω resistors placed near the host controller (not near the ADC) to absorb reflections on cables longer than 50 mm. Keep SCLK rise time slower than 20 ns where possible by adding a small series resistor at the driver output. If the SDOUT trace exceeds 25 mm, add a buffer to avoid capacitive loading that degrades the SDOUT signal rise time and causes timing errors at 200 kSps output rate.
Do not route any digital switching signals directly under the analog input traces or under the VREF decoupling capacitor - digital noise coupling into the analog input or reference directly degrades SNR and INL. Always connect unused NC pins (8, 9, 10, 21-24) to analog ground, not floating, to prevent internal coupling and noise pickup. When using ±2.5 V supplies, ensure the input common-mode voltage stays within AVDD-1.5 V and AVSS+1.5 V; violations cause linearity errors and may damage the input buffer.
Información de cumplimiento
Compliance status not confirmed in verified web data; consult Cirrus Logic product compliance certificate or contact authorised distributor for RoHS/REACH certificates. AEC-Q100 not applicable for this industrial-grade precision ADC.
