DS90C363AMTD - 18-Bit 65 MHz LVDS Transmitter | Texas Instruments
N.º de pieza: DS90C363AMTD ✓ ActivoDS90C363AMTD Descripción general
An LVDS transmitter is a high-speed interface IC that converts low-voltage differential signaling into the physical layer used by FPD-Link links. In the technology hierarchy, LVDS is a differential data transmission method, while FPD-Link is an interface protocol commonly used to connect display controllers and flat-panel panels. The DS90C363AMTD belongs to the broader interface IC category and combines parallel display-data handling with balanced, low-voltage differential outputs. This reduces signal-integrity and EMI challenges associated with long interconnects when implemented with correct PCB rules.
The principal operating characteristics are a 3 V to 3.6 V supply range, 18-bit parallel data capability, 65 MHz maximum pixel-clock operation, and three LVDS drivers. The device also supports programmable LVDS output characteristics, enabling the transmitter to be adapted to different display-link and termination requirements. It is supplied in a 48-pin TSSOP package intended for tube packing under the AMTD ordering suffix.
Technically, the DS90C363AMTD is designed to provide backward-compatible LVDS signaling for FPD-Link panel interfaces while operating from a 3.3 V system rail. The differential outputs use small signal amplitudes to support high data rates while limiting electromagnetic emissions. Clock and data lanes should be routed as controlled-impedance differential pairs, with matching termination and connector geometry maintained between the transmitter and the receiving circuitry.
Typical applications include flat-panel LCD controller interfaces, digital display panels, industrial monitors, medical display controllers, and compact embedded display systems. It is particularly useful where an 18-bit parallel pixel bus must be converted into fewer balanced LVDS lines. The 65 MHz operating limit must be checked against the target panel timing, while power sequencing, input-voltage tolerances, and panel-specific initialization requirements must be reviewed before deployment.
A critical design consideration is the relationship between data-clock timing and transmission rate. Trace skew between the clock and data channels, inadequate output-termination networks, and long unmatched stubs can impair LVDS eye quality. The transmitter should be placed near the source connector or display interface, and the datasheet timing and test-circuit recommendations should govern component placement and PCB stack-up.
This product page combines the manufacturer identification, electrical and package characteristics, interface application guidance, comparison criteria, and practical PCB considerations needed to evaluate the DS90C363AMTD as the transmitter for a 3.3 V FPD-Link display system.
Alternativas directas para DS90C363AMTD — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con DS90C363AMTD (mismo factor de forma y huella) — difiere en Package, RoHS Status, Supply Voltage.
DS90C363BMT
✅ Sustitución directaConsulte el precio
Ver hoja de datos →DS90CF363A
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
DS90C365AMTX/NOPB
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
DS90C363AMTD Especificaciones
| Product Type | Programmable LVDS FPD-Link transmitter |
| Tensión de alimentación | 3 V to 3.6 V |
| Nominal Supply Voltage | 3.3 V |
| Parallel Data Width | 18 bits |
| Maximum Pixel Clock | 65 MHz |
| Maximum Per-Channel Data Rate | 612.5 Mbps |
| Number of Drivers | 3 |
| Number of Drivers/Receivers | 3/21 |
| Interface Protocol | FPD-Link |
| Logic Family | LVDS |
| Encapsulado | 48-pin TSSOP |
| Package Body Width | 0.240 in (6.10 mm) |
| Package Body Length | 0.240 in (6.10 mm) |
| Tipo de montaje | Surface mount |
| Packing Type | Tube |
| Tensión de salida | 0.45 V differential output |
| Estado RoHS | Non-compliant |
Guía de configuración de pines de DS90C363AMTD 0.240 in (6.10 mm)
Configuración de pines para DS90C363AMTD (encapsulado 0.240 in (6.10 mm)). La numeración de pines, las funciones y los diagramas de conexión se definen en la hoja de datos del fabricante. Consúltela para conocer el footprint exacto y las directrices de soldadura.
No hay datos detallados de patillaje disponibles para DS90C363AMTD.
Consulte la hoja de datos para ver la configuración completa de patillas.
Aplicaciones típicas
DS90C363AMTD es adecuado para 6 aplicacións: Flat-Panel LCD Controller Interface, Industrial Monitor Display Link, Medical Display Controller, Embedded Human-Machine Interface, Digital Signage Controller, Test and Measurement Display.
Flat-Panel LCD Controller Interface
The DS90C363AMTD fits between a parallel display controller and an FPD-Link panel because it accepts 18 bits of display data and converts the link to differential LVDS signaling. Its 65 MHz maximum pixel clock supports common controller timing, while the three-driver architecture reduces the number of high-speed conductors reaching the panel connector. The 3 V to 3.6 V supply range also fits 3.3 V embedded display systems. Designers should verify that the panel data mapping, clock polarity, initialization sequence, and connector timing fall within the family specifications before schematic release.
Recomendado
Industrial Monitor Display Link
For industrial monitors, the DS90C363AMTD provides a compact interface between an LVDS-capable controller and a flat-panel display. The 18-bit parallel input path matches common video-controller organization, and the 612.5 Mbps maximum per-channel data rate provides the link margin associated with a 65 MHz operating ceiling. Industrial equipment may have long internal cables, noisy motors, and widely varying temperatures, making balanced signaling and controlled-impedance routing important. Validate cable length, connector loss, panel timing, and grounding against the manufacturer test recommendations.
Recomendado
Medical Display Controller
The DS90C363AMTD can serve as the display-side transmitter in a medical monitoring console when the selected panel accepts FPD-Link LVDS data. Its 18-bit parallel data width and 65 MHz clock ceiling support compact high-resolution display links, while differential signaling helps maintain signal integrity across equipment-internal interconnects. The device itself does not establish medical-system compliance, so the completed display chain must undergo electrical safety, EMC, and risk-management evaluation. Confirm panel requirements, grounding strategy, cable qualification, and fault behavior before incorporating it into a medical product.
Recomendado
Embedded Human-Machine Interface
Embedded HMIs often retain an 18-bit parallel pixel output while using a compact panel connector with differential conductors. The DS90C363AMTD bridges that interface by transmitting three LVDS data channels at up to 612.5 Mbps and supporting a 65 MHz pixel clock. This arrangement can reduce connector pin count and improve noise immunity compared with carrying all parallel pixel signals over a longer cable. The design should place the transmitter near the connector, maintain matched differential impedance, and confirm that the panel controller supports the selected data-lane organization.
Recomendado
Digital Signage Controller
The DS90C363AMTD is suitable for digital-signage controllers that drive compatible flat-panel displays through a 3.3 V FPD-Link interface. Its 18-bit input width and 65 MHz maximum clock allow the controller to use a conventional parallel pixel bus while the external cable carries balanced LVDS signals. For installations with multiple display zones, maintain consistent grounding and termination across each link and avoid adding unmodeled cable extensions. Validate the controller's refresh rate, blanking interval, panel initialization, and connector wiring against the target display before production.
Recomendado
Test and Measurement Display
A laboratory instrument can use the DS90C363AMTD to connect an embedded display controller to a compatible LVDS panel while preserving a compact internal wiring scheme. The 3 V to 3.6 V operating range supports 3.3 V logic systems, and the 65 MHz clock limit must be checked against waveform-update rates and panel timing. Keep high-current switching stages and precision analog sections physically separated from the differential link, and follow controlled-impedance layout rules to prevent display-related noise from disturbing measurement accuracy.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para DS90C363AMTD — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | DS90C363BMT | DS90CF363A | DS90C365AMTX/NOPB |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-pin TSSOP | 48-pin TSSOP | 48-pin TSSOP | 48-pin TSSOP |
| Product Function | Programmable LVDS FPD-Link transmitter | DS90C363 family transmitter | 3.3 V LVDS transmitter family | 3.3 V LVDS flat-panel transmitter |
| Supply Voltage Range | 3 V to 3.6 V | 3.3 V family | 3.3 V | 3.3 V |
| Maximum Data Rate | 612.5 Mbps | 612.5 Mbps | 612.5 Mbps | 612.5 Mbps |
| Logic Interface | LVDS | LVDS | LVDS | LVDS |
Diferenciadores clave
- Specific 18-bit DS90C363 transmitter organization (frente a DS90C365AMTX/NOPB)
- Tube-packed exact ordering option (frente a DS90C363BMT)
- Documented maximum channel rate (frente a DS90CF363A)
Notas de diseño
Route every LVDS output as a controlled-impedance differential pair with closely matched length and geometry. Keep the pairs free of stubs, test pads, and abrupt reference-plane changes. Follow the Texas Instruments DS90C363 manufacturer datasheet test-circuit layout when selecting spacing, pair width, via construction, and connector escape geometry; otherwise a nominal 48-pin TSSOP footprint alone does not guarantee acceptable signal integrity.
Do not assume that every 48-pin TSSOP member of the DS90C363, DS90CF363, or DS90C365 families is electrically and pin-for-pin interchangeable. Check the exact pin names, clock timing, panel data mapping, supply limits, initialization sequence, and ordering suffix against the official device documentation. A footprint match protects PCB assembly only; functional compatibility requires a complete interface review.
The transmitter supports a 65 MHz pixel clock and up to 612.5 Mbps per data channel, so clock-to-data skew and channel-to-channel skew can affect the receiving eye. Match clock and data routing characteristics, keep the transmitter close to the panel connector, and evaluate the complete cable, termination, connector, and receiver as one channel. Use the manufacturer's datasheet timing and test setup as the reference for compliance measurements.
Place local supply decoupling at the transmitter's power pins and provide a continuous, low-impedance ground return for all differential pairs. Confirm that the 3.3 V rail remains between 3 V and 3.6 V during startup, load transients, and temperature extremes. Because the available operating-temperature range is not identified for this exact ordering option, obtain that limit from the manufacturer before conducting worst-case qualification.
Información de cumplimiento
The available component listing explicitly identifies the DS90C363AMTD as RoHS non-compliant. No additional compliance conclusion is made for REACH, AEC-Q100, lead-free construction, halogen content, or conflict minerals.
