HCI-CPU-A9654 - AMD EPYC 9654 96-Core 2.4GHz CPU | Cisco
N.º de pieza: HCI-CPU-A9654 ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $13905.27 | $13.905,27 |
| 10 | $13509.99 | $135.099,90 |
| 100 | $13114.71 | $1.311.471,00 |
| 500 | $12719.43 | $6.359.715,00 |
| 1.000 | $12324.15 | $12.324.150,00 |
HCI-CPU-A9654 Descripción general
A server processor (CPU) is the central compute element of a data center server, sitting at the top of the compute hierarchy: microprocessor -> server processor -> compute node -> server -> data center infrastructure. The EPYC 9004 series represents AMD's fourth-generation server platform, code-named Genoa, built to serve modern cloud, virtualization, and enterprise workloads.
Key features of this part include an industry-leading 96-core density in a single socket, a large 384 MB L3 cache that reduces memory latency for database and analytics workloads, 12-channel DDR5-4800 memory support (up to 460.8 GB/s bandwidth per socket), and PCIe Gen5 I/O for high-speed NVMe storage and 400G networking. The 5nm chiplet architecture with Zen 4 cores balances per-core throughput against energy efficiency.
Architecturally, the EPYC 9654 uses multiple Zen 4 CCD chiplets bonded to a central I/O die on the SP5 socket, providing 128 usable PCIe Gen5 lanes per processor - roughly double the I/O of competing single-socket platforms - which reduces the need for additional switch silicon in storage and composable infrastructure designs.
Typical applications include Cisco UCS X-Series and HCI (hyperconverged infrastructure) nodes, large-scale virtualization and VDI farms, in-memory and relational databases, AI/ML data preprocessing, and high-density cloud-native container platforms where core count and memory bandwidth dominate performance.
Design and deployment consideration: at 360W TDP, this processor requires validated server-level cooling and power delivery; it must only be installed in Cisco platforms listed on the Cisco UCS Hardware Compatibility List, as firmware and thermal profiles are platform-specific.
This page synthesizes distributor pricing, Cisco SKU cross-references, and deployment guidance not found in the manufacturer datasheet. Pricing shown as of 2026-10-19.
Alternativas directas para HCI-CPU-A9654 — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
UCS-CPU-A9654
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
UCSX-CPU-A9654
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
EPYC 9654
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HCI-CPU-A9654 Especificaciones (publicadas por el fabricante)
| Processor Model | AMD EPYC 9654 (Cisco OEM HCI-CPU-A9654) |
| CPU Core Count | 96 cores |
| Thread Count | 192 threads |
| Base Clock | 2.4 GHz |
| L3 Cache | 384 MB |
| TDP | 360 W |
| Memory Support | DDR5-4800 MT/s |
| Memory Channels | 12 channels |
| Socket | SP5 (LGA-6096) |
| Processor Series | AMD EPYC 9004 (Genoa, 4th Gen) |
| Core Architecture | Zen 4 |
| PCIe Support | PCIe Gen5 |
| OEM Platform | Cisco UCS / Hyperflex (HCI) |
| Tipo de memoria | DDR5 ECC Registered DIMM |
Interfaces y conectores de HCI-CPU-A9654
HCI-CPU-A9654 expone las siguientes interfaces y conectores según lo publicado por el fabricante: PCIe. El patillaje de la cabecera de expansión, la numeración de pines de los conectores y los límites eléctricos se definen en la documentación del fabricante.
| PCIe | PCIe Gen5 |
Consulte la documentación del fabricante para ver el patillaje completo del conector de expansión y la numeración de pines del conector.
Aplicaciones típicas
HCI-CPU-A9654 es adecuado para 6 aplicacións: Hyperconverged Infrastructure (HCI) Nodes, Large-Scale Server Virtualization, Database and Analytics Servers, Private and Hybrid Cloud Compute, AI/ML Data Preprocessing and Inference, Software-Defined Storage (SDS) Nodes.
Hyperconverged Infrastructure (HCI) Nodes
The HCI-CPU-A9654 is the flagship compute element for Cisco HyperFlex nodes, where 96 Zen 4 cores per socket allow a single 1U/2U appliance to host hundreds of VMs alongside the HCI storage stack. The 384 MB L3 cache keeps virtualization overhead and distributed-storage I/O threads resident in cache, while 12-channel DDR5-4800 provides the memory bandwidth the storage data path needs. At 360W TDP per socket, HCI clusters should be sized with validated Cisco thermal modules; in dual-socket nodes, budget roughly 720W for processors alone. Because the SKU is Cisco-qualified, firmware, BIOS, and HCL validation are pre-cleared, shortening deployment time versus retail silicon.
Recomendado
Large-Scale Server Virtualization
For VMware vSphere, Microsoft Hyper-V, and KVM farms, the EPYC 9654's 96 cores and 192 threads maximize VM-per-node density and reduce per-VM licensing overhead in core-unlicensed stacks. The 2.4 GHz base clock across all 96 cores guarantees consistent per-VM SLAs under full population, unlike boost-dependent SKUs. According to xsnet.com.au, this SKU was explicitly positioned for mixed virtualization workloads in Cisco UCS X-Series. Pair with 12-channel DDR5-4800 RDIMMs populated evenly to reach full bandwidth; oversized VMs benefit from the 384 MB L3 cache shared across chiplets. The main trade-off versus higher-clock, fewer-core 9004 SKUs is single-thread latency, which matters for latency-sensitive VMs.
Recomendado
Database and Analytics Servers
In-memory and relational databases exploit the EPYC 9654's 384 MB L3 cache and 460.8 GB/s per-socket memory bandwidth (12x DDR5-4800) to keep hot data sets close to cores. Query-parallel engines scale across 96 cores, and the chiplet design keeps cache coherent at high core counts. Cisco's own positioning of this SKU for database workloads (per xsnet.com.au and Avendor) reflects validated memory population rules and firmware. Estimated: a 1.5 TB hot working set in a dual-socket 3 TB node fits largely in combined L3 plus DRAM at near-peak bandwidth. Use 3DS RDIMMs for maximum capacity, and verify per-core database licensing economics against fewer-core SKUs before standardizing.
Recomendado
Private and Hybrid Cloud Compute
Cloud service providers and enterprise private clouds use the HCI-CPU-A9654 to raise tenant density per rack-unit. With 128 PCIe Gen5 lanes per socket on SP5, a single node can attach NVMe storage fabrics, GPUpassthrough devices, and 100G/400G NICs without PCIe switch silicon, cutting BOM cost and latency. The 5nm Zen 4 chiplets deliver strong performance-per-watt, an important metric at data center scale despite the 360W TDP. Per AMD's product page, the 9004 series targets business-critical workloads with energy efficiency emphasis. Deploy in Cisco UCS pools for uniform firmware baselines; use NPS/BIOS profiles to cap PPT in power-constrained facilities.
Recomendado
AI/ML Data Preprocessing and Inference
While GPU acceleration handles model training, the EPYC 9654 excels at data ingestion, feature engineering, and CPU inference. Ninety-six cores parallelize ETL pipelines, and 12-channel DDR5-4800 feeds dataloaders at up to 460.8 GB/s per socket, keeping accelerators saturated. The large 384 MB L3 cache benefits batch-scoring of tree-based models (XGBoost, LightGBM), which remain memory-latency sensitive. Estimated: CPU-side tokenization and embedding retrieval for LLM serving pipelines scale nearly linearly across the 192 threads. Cisco UCS platforms carrying this SKU offer validated PCIe Gen5 GPU companion options; plan lane allocation so GPUs and NVMe do not contend for the same PCIe Gen5 root complex groups.
Recomendado
Software-Defined Storage (SDS) Nodes
SDS platforms (Ceph, vSAN, StorageSpaces) are I/O and core-hungry: replication, erasure coding, and checksumming consume cores continuously. The EPYC 9654's 96 cores let one node drive high NVMe densities, and PCIe Gen5 connectivity attaches 24+ U.2 drives per socket with headroom for front-side 100G fabrics. Twelve DDR5-4800 channels sustain metadata caches; the 384 MB L3 absorbs journal and hash-table working sets. Estimated: dedicating 8-12 cores per NVMe group is a common Ceph sizing starting point, making a dual-socket 192-thread node suitable for all-flash clusters. Cisco HCL-validated thermal profiles are essential because sustained storage workloads hold the processor near its full 360W envelope.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para HCI-CPU-A9654 — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | UCS-CPU-A9654 | UCSX-CPU-A9654 | EPYC 9654 (100-000000454) |
|---|---|---|---|---|
| Package | SP5 (LGA-6096) | SP5 (LGA-6096) - same | SP5 (LGA-6096) - same | SP5 (LGA-6096) - same |
| Brand / OEM | Cisco (OEM SKU) | Cisco (OEM SKU) | Cisco (OEM SKU) | AMD (retail) |
| Cores / Threads | 96 / 192 | 96 / 192 | 96 / 192 | 96 / 192 |
| Base Clock | 2.4 GHz | 2.4 GHz | 2.4 GHz | 2.4 GHz |
| L3 Cache | 384 MB | 384 MB | 384 MB | 384 MB |
| TDP | 360 W | 360 W | 360 W | 360 W |
| Memory Support | 12ch DDR5-4800 | 12ch DDR5-4800 | 12ch DDR5-4800 | 12ch DDR5-4800 |
| Target Platform | Cisco HyperFlex (HCI) | Cisco UCS C-Series | Cisco UCS X-Series | Any SP5 server |
Diferenciadores clave
- Maximum core density of the EPYC 9004 family (frente a Lower-core 9004-series SKUs (e.g., EPYC 9554))
- Cisco OEM qualification for HCI platforms (frente a EPYC 9654 (100-000000454) retail)
- 384 MB L3 cache for memory-bound workloads (frente a UCS-CPU-A9654)
Notas de diseño
At 360W TDP per socket, the HCI-CPU-A9654 demands a Cisco-validated heatsink and airflow profile. Estimated: a dual-socket node dissipates ~720W from processors alone; chassis fans and rear-door heat exchangers must be sized for this plus DIMM and drive heat. Never reuse heatsinks from 240W-class SKUs - contact area and heat pipe count differ. Confirm the exact validated heatsink part number via the Cisco UCS HCL before deployment, as it is not published in the distributor listings.
The HCI-CPU-A9654 is a Cisco OEM SKU: it is warranted and firmware-locked for Cisco UCS/HyperFlex platforms. Installing it in third-party SP5 boards risks voided warranty and BIOS compatibility issues. Conversely, mixing OEM prefixes (HCI/UCS/UCSX) across chassis families should be verified against the Cisco UCS HCL (version 4.5.6, database updated 2026-10-07) for firmware and thermal support before purchase.
Provision server power for full 360W per socket sustained - storage and HCI workloads hold the part near TDP continuously. Estimated: a dual-socket node with 24 populated DDR5 DIMMs, 24 NVMe drives, and 2x 100G NICs draws roughly 1.6-1.9 kW typical, so 2000W+ PSU configurations (or redundant 1600W pairs) are standard. Use Cisco IMC power capping to enforce facility power budgets rather than relying on CPU P-state throttling alone.
Memory population matters: to achieve DDR5-4800 on SP5, populate all 12 channels per socket with identical RDIMMs (one DIMM per channel). Uneven population drops both capacity interleaving and rated speed. For maximum capacity beyond standard RDIMMs, use 3DS RDIMMs. Follow the Cisco HCL memory population tables - SP5 does not rate DDR5-4800 at two DIMMs per channel.
Información de cumplimiento
Compliance data not present in the provided distributor listings or AMD product page snippet. Server processors are IT equipment (not AEC-Q100 automotive). Consult AMD/Cisco product compliance documentation.