HI5762/6INZ - Dual 10-Bit 60MSPS ADC w/Internal VREF | Renesas
N.º de pieza: HI5762/6INZ ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.85 | $1.385,00 |
| 500 | $11.4 | $5.700,00 |
| 1.000 | $9.95 | $9.950,00 |
HI5762/6INZ Descripción general
What is a pipelined ADC? A pipelined analog-to-digital converter is a multi-stage architecture that converts analog signals to digital codes by passing the input through a cascade of low-resolution stages, each producing a partial conversion and feeding a residue to the next stage. Compared with flash or successive-approximation (SAR) ADCs, pipelined converters deliver much higher sampling rates (tens to hundreds of MSPS) at moderate resolution (8-14 bits), making them the workhorse of high-speed data acquisition. The HI5762 sits in the ADC -> data converter -> data acquisition IC -> signal processing semiconductor taxonomy.
Key features of the HI5762/6INZ include 60 MSPS sampling rate per channel (dual simultaneous sampling), 10-bit resolution, internal 2.5 V bandgap voltage reference, CMOS-compatible digital outputs, low power consumption (typical 200 mW per channel at 60 MSPS), and a wide analog input bandwidth that supports IF undersampling. The pipelined architecture provides inherent sample-and-hold behavior on each channel, simplifying front-end driver design.
Architecturally, the HI5762 combines two cores of the HI5767 single-channel 10-bit 60 MSPS ADC into a single die. This integration halves board space and improves channel-to-channel matching for I/Q demodulation, dual-antenna diversity receivers, and correlated multi-channel instrumentation. The internal reference eliminates the drift and noise issues of external references, though external reference operation is supported for applications requiring absolute accuracy.
Typical applications include communications base-station receivers, digital oscilloscopes, medical imaging front-ends, radar signal processing, and high-speed instrumentation. The simultaneous dual-channel sampling makes the HI5762/6INZ particularly well suited for I/Q quadrature demodulation in software-defined radio (SDR) and diversity reception.
When designing with this ADC, route analog and digital grounds separately and join them at a single point under the IC's exposed pad (where present). The 44-MQFP package has moderate thermal resistance; airflow is recommended when both channels sample at 60 MSPS continuously in enclosed enclosures.
This page synthesizes distributor pricing as of 2026-10-13, drop-in alternatives, pinout, and practical design notes not found in the manufacturer datasheet alone.
Alternativas directas para HI5762/6INZ — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con HI5762/6INZ (mismo factor de forma y huella) — difiere en Architecture, Input Type, Number of Channels, Process Technology.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
HI5762/6IN
✅ Sustitución directa✓ En stock
$9.95 / unidad
Ver hoja de datos →HI5762/6CB
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
HI5762/6CB-T
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
HI5762/6INZ Valores máximos y características eléctricas
| Manufacturer | Renesas Electronics (formerly Intersil) |
| Part Number | HI5762/6INZ |
| Resolución | 10 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Frecuencia de muestreo | 60 MSPS per channel |
| Architecture | Pipelined |
| Input Type | Differential / Single-ended (analog input) |
| Data Interface | Parallel (CMOS outputs) |
| Voltage Reference | Internal (with external override option) |
| Encapsulado / Carcasa | 44-MQFP (10x10 mm) |
| Packaging | Tray |
| Temperatura de funcionamiento | -40C to +85C |
| Process Technology | CMOS |
| Número de pines | 44 |
| Tipo de montaje | Surface Mount |
Guía de configuración de pines de HI5762/6INZ 44-mqfp (10x10 mm)
Configuración de pines para HI5762/6INZ (encapsulado 44-mqfp (10x10 mm)). Este componente analógico presenta pines de entrada, salida y alimentación. Consulte la hoja de datos del fabricante para conocer las configuraciones de los pines de ajuste de offset, compensación y habilitación. Ideal para circuitos de acondicionamiento de señal y amplificadores.
No hay datos detallados de patillaje disponibles para HI5762/6INZ.
Consulte la hoja de datos para ver la configuración completa de patillas.
Aplicaciones típicas
HI5762/6INZ es adecuado para 6 aplicacións: Software-Defined Radio (SDR) I/Q Demodulation, Digital Oscilloscope and Data Acquisition Front-End, Communications Base-Station Receiver, Medical Imaging Front-End (Ultrasound Beamforming), Radar and Lidar Signal Processing, High-Speed Test and Measurement Instrumentation.
Software-Defined Radio (SDR) I/Q Demodulation
The HI5762/6INZ dual 10-bit 60 MSPS simultaneous-sampling ADC is purpose-built for SDR I/Q demodulation in quadrature receivers. Its two matched pipelined cores digitize the in-phase and quadrature baseband signals at the same instant, preserving phase coherence required for downstream digital down-conversion. The internal voltage reference eliminates reference drift between channels, and the 60 MSPS per-channel rate comfortably handles IF frequencies up to ~25 MHz with proper anti-alias filtering.
Recomendado
Digital Oscilloscope and Data Acquisition Front-End
In digital storage oscilloscopes and high-speed data acquisition cards, the HI5762/6INZ provides two correlated 10-bit 60 MSPS digitizer channels on a single die, halving board space versus two single-channel ADCs. The pipelined architecture delivers excellent dynamic performance at full sampling rate, and the CMOS-compatible parallel outputs stream directly into an FPGA for real-time triggering and display. Internal VREF simplifies calibration by removing external reference drift over temperature.
Recomendado
Communications Base-Station Receiver
Base-station receivers in cellular and fixed-wireless systems use dual-channel ADCs to digitize diversity or I/Q paths at IF. The HI5762/6INZ's industrial -40C to +85C temperature range and 60 MSPS sampling comfortably handle 30+ MHz intermediate frequencies, while its 10-bit resolution provides adequate dynamic range for demodulating QAM/QPSK signals. The /6 annealed variant adds extra reliability for outdoor-mounted base-station hardware exposed to thermal cycling.
Recomendado
Medical Imaging Front-End (Ultrasound Beamforming)
Ultrasound beamforming systems require many simultaneous-sampling ADC channels operating at 30-65 MSPS to capture RF echoes from transducer arrays. The HI5762/6INZ dual-channel integration reduces per-channel cost and PCB area, and its pipelined architecture preserves phase accuracy across channels - critical for beamforming calculations. The internal VREF and low power consumption (about 200 mW per channel at 60 MSPS) ease thermal management in dense multi-channel probe heads.
Recomendado
Radar and Lidar Signal Processing
Radar and lidar receivers digitize return-signal phase and amplitude at high sample rates for FFT-based range-Doppler processing. The HI5762/6INZ dual 10-bit 60 MSPS channels enable matched I/Q sampling of the IF stage, with its CMOS outputs feeding directly into an FPGA DSP pipeline. The industrial temperature range and the /6 anneal option suit outdoor-mounted automotive and aerospace radar platforms.
Recomendado
High-Speed Test and Measurement Instrumentation
Automated test equipment, spectrum analyzers, and protocol analyzers require wide-bandwidth dual-channel digitization for time-correlated measurements such as jitter analysis, two-port network analysis, and differential signal capture. The HI5762/6INZ dual simultaneous 10-bit 60 MSPS channels deliver 30 MHz analog input bandwidth with matched gain and offset, while the internal VREF reduces calibration cycles over temperature. The /6INZ variant is preferred for production-floor ATE requiring industrial-grade reliability.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para HI5762/6INZ — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | HI5762/6IN | HI5762/6CB | HI5762/6CB-T |
|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 44-MQFP (10x10) | 44-MQFP (10x10) - same | 44-MQFP (10x10) - same | 44-MQFP (10x10) - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit |
| Sampling Rate | 60 MSPS | 60 MSPS | 60 MSPS | 60 MSPS |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) |
| Voltage Reference | Internal | Internal | Internal | Internal |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Process Grade / Screening | Annealed (/6) high-reliability | Annealed (/6) | Standard commercial | Standard commercial |
| Packaging Media | Tray | Tray | Tray | Tape & Reel |
Diferenciadores clave
- Only dual 10-bit 60 MSPS ADC in the HI5762 family offered with industrial -40C to +85C AND annealed (/6) high-reliability screening (frente a HI5762/6CB)
- Same-die pin compatibility across the entire HI5762/6INZ family (frente a HI5762/6IN)
- Higher resolution than common dual 8-bit 60 MSPS competitors (frente a AD9288 (cross-brand))
Notas de diseño
Use separate analog and digital ground planes that join at a single point directly under the HI5762/6INZ IC. Place the input anti-aliasing RC network as close as possible to each analog input pin. Route the 60 MSPS CMOS parallel output bus with matched trace lengths (within ~2 mm) to the receiving FPGA to minimize skew-induced sampling errors. Add a 0.1 uF ceramic decoupling capacitor within 5 mm of each supply pin and a bulk 10 uF tantalum at the board entry.
Estimated: at 60 MSPS CMOS output toggle rate, each parallel output trace behaves as a short transmission line above ~25 mm length. Apply 22-33 ohm series damping resistors at the HI5762/6INZ output pins when traces exceed this length, to limit overshoot and ringing into the FPGA. Keep clock traces short and route them perpendicular to output buses to avoid coupling. If the application drives long external cables, add an additional buffer/driver between the ADC and the connector.
The 44-MQFP package has a theta_JA of approximately 50 C/W in still air, dissipating around 400 mW total (200 mW per channel at 60 MSPS). For continuous 60 MSPS dual-channel operation in an enclosed chassis without airflow, junction temperature rise above ambient is roughly 20 C, well within the 125 C maximum. Provide at least 100 LFM airflow if the board is mounted in a sealed enclosure or if the surrounding components push ambient above 60 C.
Do not exceed the absolute maximum analog input voltage (consult datasheet section 'Absolute Maximum Ratings'). Drive the analog inputs through a low-impedance op-amp buffer (such as the ADA4857 or AD8055) rather than a high-impedance source, to avoid sampling-charge-induced distortion. When using the internal reference, bypass the REFOUT pin with a 0.1 uF ceramic plus 10 uF tantalum to ground. The /6INZ suffix indicates an annealed variant - do not confuse with the standard non-annealed HI5762/6IN if your application requires the burn-in screening.
Información de cumplimiento
Compliance data not explicitly provided in the verified web data for HI5762/6INZ; recommend confirming RoHS/REACH/AEC-Q100 status directly with Renesas product documentation before use in automotive or aerospace qualified designs. Conflict-mineral compliance assumed per standard Renesas policy but not explicitly confirmed in the provided data.
