JMB582 - PCIe Gen3x1 to 2-Port SATA 6Gb/s Bridge | JMicron
N.º de pieza: JMB582 ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $2.85 | $2,85 |
| 10 | $2.55 | $25,50 |
| 100 | $2.2 | $220,00 |
| 500 | $1.95 | $975,00 |
| 1.000 | $1.75 | $1.750,00 |
JMB582 Descripción general
A PCIe-to-SATA bridge controller is an interface IC that translates between the PCI Express host bus protocol and the Serial ATA (SATA/AHCI) device protocol. In the storage-signal-chain hierarchy it sits between the host PCIe root port and SATA SSD/HDD endpoints, allowing motherboards, embedded x86 platforms, IPC, and servers to expand the number of SATA ports without changing the host chipset.
Key features include a PCIe Gen3 x1 upstream port (compatible with PCIe 3.1a and backward compatible with PCIe 2.0/1.x), two independent SATA 6Gb/s host ports, support for both AHCI and legacy IDE programming interfaces, NCQ (Native Command Queuing), TRIM pass-through to SSDs, and PCIe link-layer power-saving modes for low idle power. The integrated PHYs eliminate external PHY chips, reducing BOM cost and board area.
Architecturally, the JMB582 uses JMicron in-house PCI Express and SATA PHY macrocells with a packet-based protocol bridge. The upstream link nearly saturates the PCIe Gen3 x1 line bandwidth (approximately 985 MB/s usable), which is sufficient to drive two SATA 6Gb/s devices (up to about 550 MB/s each) in typical workloads. Port multiplier support allows additional drives per SATA port where required.
Typical applications include M.2-to-SATA and PCIe-to-SATA add-in cards (such as the Seeed ODYSSEY-X86J4105 expansion and Waveshare dual M.2 SATA expander), NAS/home-server storage expansion, industrial PCs and consumer electronics requiring extra SATA connectivity.
Design-wise, place the 3.3V input decoupling close to the QFN power pins, route the PCIe and SATA differential pairs with 100-ohm controlled impedance, and confirm the host BIOS exposes AHCI mode for TRIM support.
This page adds value beyond the JMicron datasheet by synthesizing distributor availability, orderable variant cross-references (JMB582-QHCA0A, JMB582-QHCB0A), design notes, and application guidance in one place.
Alternativas directas para JMB582 — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con JMB582 (mismo factor de forma y huella) — difiere en Function, Host Interface, Mounting Type, Package, RoHS Status.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
JMB582-QHCA0A
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
JMB582-QHCB0A
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
JMB582 Especificaciones
| Función | PCIe to SATA/AHCI bridge controller |
| Host Interface | PCIe Gen3 x1 (compatible with PCIe 3.1a) |
| Device Interface | 2x SATA 6Gb/s ports |
| SATA Compliance | SATA Revision 3.2 |
| Programming Interfaces | AHCI and legacy IDE mode |
| NCQ Support | Yes (Native Command Queuing) |
| TRIM Support | Yes (SSD TRIM pass-through) |
| Hot Plug | Supported |
| Port Multiplier | Supported on SATA host ports |
| Power Saving | PCIe link layer power saving mode |
| Integrated PHYs | PCIe PHY and SATA PHY (self-designed by JMicron) |
| Encapsulado | QFN-48, 6x6 mm |
| Tipo de montaje | Surface Mount (SMT) |
| Estado RoHS | Compliant (per JLCPCB listing) |
| Typical Applications | PC, mobile, servers, IPC, consumer electronics |
| PCI ID | VID 197B (JMicron), per PCI-SIG listing |
Guía de configuración de pines de JMB582 qfn-48, 6x6 mm
Configuración de pines para JMB582 (encapsulado qfn-48, 6x6 mm). La numeración de pines, las funciones y los diagramas de conexión se definen en la hoja de datos del fabricante. Consúltela para conocer el footprint exacto y las directrices de soldadura.
No hay datos detallados de patillaje disponibles para JMB582.
Consulte la hoja de datos para ver la configuración completa de patillas.
Aplicaciones típicas
JMB582 es adecuado para 6 aplicacións: PCIe to SATA Add-in Cards, M.2 to SATA Expansion Adapters, NAS and Home Server Storage Expansion, Industrial PCs (IPC) and Embedded x86, Consumer Electronics and Set-top Storage, Server and Mobile Storage Upgrade Modules.
PCIe to SATA Add-in Cards
The JMB582 is the de-facto chipset for 2-port PCIe 3.0 x1 SATA III controller cards such as the IO Crest SI-PEX40148, Kalea-Informatique low/high-profile cards, and PINE64's dual SATA-III interface card. Its PCIe Gen3 x1 upstream nearly saturates the lane (~985 MB/s), feeding two independent 6Gb/s SATA channels with AHCI, NCQ, TRIM, and hot plug support, so drives appear as native AHCI devices without port-multiplier overhead. Card designers benefit from the single-chip integration of both PCIe and SATA PHYs, minimizing BOM count, and the PCIe link-layer power saving mode keeps idle card draw around 3 W or less in homelab/NAS deployments.
Recomendado
M.2 to SATA Expansion Adapters
M.2 slots on mini-PCs and x86 SBCs expose PCIe Gen3 x1 lanes that the JMB582 converts into two M.2 SATA (B-key) or standard SATA ports, as implemented on the Waveshare PCIe-SATA-M2-2P-A expander and the Seeed ODYSSEY-X86J4105 expansion board (DigiKey 103990565). The QFN-48 6x6 mm footprint fits compact adapter PCBs, and integrated PHYs avoid extra retiming parts. Because the bridge presents a standard AHCI controller (PCI ID 197B), it works plug-and-play with in-box Windows and Linux drivers, and TRIM pass-through keeps attached SSDs healthy - a key requirement for long-lived embedded storage upgrades.
Recomendado
NAS and Home Server Storage Expansion
For Unraid, TrueNAS, and homelab servers, JMB582-based cards add two drives to motherboards with limited SATA connectors. Community deployments report only ~3 W added idle power and stable parity-sync operation across the PCIe Gen3 x1 link, whose ~900 MB/s usable bandwidth comfortably serves two simultaneous HDD streams (HDDs rarely exceed 280 MB/s each). NCQ and AHCI compliance ensure correct queue behavior under ZFS/Unraid workloads, and hot plug supports drive swaps in hot-swap bays. For arrays beyond four to five drives, designers should step up to the PCIe x2, 5-port JMB585 instead of cascading port multipliers.
Recomendado
Industrial PCs (IPC) and Embedded x86
Industrial PCs and embedded x86 controllers frequently need extra SATA channels for logging, vision data capture, or local RAID-1 mirroring but expose only one free PCIe lane. The JMB582 addresses this with a Gen3 x1 upstream, two independent SATA 6Gb/s ports, and JMicron datasheet-listed suitability for IPC applications. Its RoHS-compliant QFN-48 SMT package supports standard reflow assembly, and legacy IDE mode compatibility allows integration into older software environments that predate AHCI. The bridge's port multiplier support also permits fan-out to additional drives where a single-cable backplane is used.
Recomendado
Consumer Electronics and Set-top Storage
JMicron's datasheet explicitly lists consumer electronics among JMB582 target markets: NAS-style media players, DVRs, and set-top boxes that add a 2.5-inch SATA drive over a spare PCIe lane. The controller's PCIe link-layer power saving mode matters in always-on consumer devices, cutting bridge idle power, while full SATA 3.2 compliance guarantees interoperability with commodity 2.5-inch HDDs and SSDs. Because it transmits in both AHCI and legacy IDE modes, firmware teams on cost-sensitive SoC platforms without a mature AHCI stack can still bring up storage quickly.
Recomendado
Server and Mobile Storage Upgrade Modules
The JMicron datasheet names servers and mobile platforms as JMB582 application areas. In 1U/2U servers, a JMB582-based riser adds two hot-plug SATA ports per free x1 slot for boot drives or cache devices. In mobile/compact compute modules, the 6x6 mm QFN-48 package and single-chip PHY integration enable thin M.2-to-SATA carrier boards. TRIM support preserves SSD endurance and sustained-write performance across both scenarios, and PCI-SIG membership (VID 197B) ensures the device ID ecosystem is recognized by mainstream operating systems without custom drivers.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para JMB582 — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | JMB582-QHCA0A | JMB582-QHCB0A | JMB585 |
|---|---|---|---|---|
| Brand | JMicron Technology | JMicron Technology | JMicron Technology | JMicron Technology |
| Host Interface | PCIe Gen3 x1 | PCIe Gen3 x1 | PCIe Gen3 x1 | PCIe Gen3 x2 |
| SATA Ports | 2 x SATA 6Gb/s | 2 x SATA 6Gb/s | 2 x SATA 6Gb/s | 5 x SATA 6Gb/s |
| TRIM / NCQ / Hot Plug | Yes / Yes / Yes | Yes / Yes / Yes | Yes / Yes / Yes | Yes / Yes / Yes |
| Port Multiplier Support | Yes | Yes | Yes | Yes |
| PCI ID (VID) | 197B (JMicron) | 197B (JMicron) | 197B (JMicron) | 197B (JMicron) |
| Typical Use Case | 2-drive PCIe/M.2 SATA expansion | 2-drive PCIe/M.2 SATA expansion | 2-drive PCIe/M.2 SATA expansion | 4-5 drive NAS / multi-bay systems |
Diferenciadores clave
- Native 2 independent SATA channels on a single PCIe lane (frente a ASM1064 (functional alternative))
- Single-chip integration of PCIe and SATA PHYs (frente a JMB585)
- Dual AHCI + legacy IDE host interface support (frente a JMB585)
Notas de diseño
Route the PCIe Gen3 x1 differential pair (TX/RX) and both SATA 6Gb/s differential pairs as 100-ohm coupled lines with length matching within 5 mils intra-pair. Keep each pair away from clock and power switching traces by at least 3x the trace width. The JMB582 integrates both PHYs, so AC-coupling capacitors (typically 100 nF, placed near the transmitter side) must be included per PCIe and SATA serial specifications on every differential line.
Decouple each QFN-48 power domain (3.3V IO and the lower-voltage core/PHY rails identified in the datasheet) with at least one 100 nF ceramic per pin group plus bulk 10 uF per rail, placed within 2 mm of the pins. Because the PCIe link-layer power saving mode lets the chip enter low-power states, ensure power-good behavior during rapid L0s/L1 transitions - inadequate bulk capacitance is the most common cause of link retraining errors on bridge cards.
Enable AHCI mode (not IDE compatibility mode) in the host BIOS or TRIM will not pass through to attached SSDs, degrading write performance over time. Also avoid designs that hang a SATA port multiplier off the JMB582 to squeeze in more than 2 drives on a x1 link - community testing (Reddit homelab/unRAID threads) shows PM-based multi-drive cards are the primary failure and instability source; use the PCIe x2 JMB585 for higher port counts instead.
For the QFN-48 6x6 mm package, provide a solid ground plane under the die and stitch the center exposed pad (where present per datasheet) with a 3x3 via array to ground for thermal and return-path integrity. Connect reference clocks with series termination per the host REFCLK topology (common clock vs SRIS) chosen - mismatches here are a frequent root cause of PCIe Gen3 eye-diagram failures in add-in-card designs.
Información de cumplimiento
RoHS compliance stated on JLCPCB Assembly listings (QFN48 SMT ROHS). REACH, halogen-free, and conflict-minerals status not stated in provided data; consult JMicron product environmental documents.
