LT1236ACS8-5 - 5V Precision Buried Zener Reference | Analog Devices
N.º de pieza: LT1236ACS8-5 ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $6.5 | $6,50 |
| 10 | $5.85 | $58,50 |
| 100 | $5.2 | $520,00 |
| 500 | $4.7 | $2.350,00 |
| 1.000 | $4.25 | $4.250,00 |
LT1236ACS8-5 Descripción general
What is a buried-Zener voltage reference? A buried-Zener reference uses a subsurface avalanche breakdown junction rather than a bandgap or surface Zener. The subsurface architecture eliminates surface breakdown noise and stability problems, and delivers better temperature drift and time stability than even the best bandgap references. In the power-management IC hierarchy, voltage references sit alongside LDO regulators, supervisors and ADC/DAC converters, providing the precision DC anchor that every high-accuracy analog signal chain requires.
Key specifications include 5 ppm/°C maximum temperature coefficient (C-grade), 4 ppm p-p noise (0.1 Hz to 10 Hz), 1.5 µVrms wideband noise, ±0.05% initial accuracy, 10 mA output current with source/sink capability, and 7.2 V to 40 V supply range. The LT1236 series is also nearly immune to input voltage variations due to its high PSRR.
Architecturally, the LT1236 uses an on-chip buried-Zener diode, a temperature-compensation network, and a buffered output stage capable of both sourcing and sinking current. The dual output-capable topology allows the 10 V variant to operate as a shunt regulator (two-terminal Zener) with the same precision specifications, while the 5 V variant operates as a series reference with VIN headroom of 7.2 V minimum.
Typical applications include high-resolution 16-/18-bit ADC and DAC reference inputs, precision instrumentation and digital multimeters, industrial process control loops, weigh scales and strain-gauge bridges, and precision voltage regulators. Designers also use it as a system-wide calibration reference in test-and-measurement equipment.
When designing with the LT1236ACS8-5, respect the 7.2 V minimum supply and use a 1 µF to 10 µF output capacitor close to the VOUT pin for stability. Decouple VIN with 0.1 µF in parallel with 1 µF, keep trace capacitance on the noise-reduction (NR) pin minimal, and avoid sinking more than 10 mA continuously to prevent self-heating drift.
This page synthesizes Analog Devices datasheet specifications, distributor pricing, drop-in cross-references and practical PCB design notes that are not found in the standalone manufacturer datasheet PDF, giving engineers a single source for selection, sourcing and board-level implementation.
Alternativas directas para LT1236ACS8-5 — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
LT1236AIS8-5
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
LT1236ACS8-5#PBF
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
LT1236ACS8-5#TR
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
LT1236ACS8-5#TRPBF
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
LT1236BCS8-5
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
LT1236ACS8-5 Especificaciones
| Reference Type | Series, Buried Zener |
| Tensión de salida | 5.000 V (fixed) |
| Initial Accuracy | ±0.05% |
| Temperature Coefficient (C-grade) | 5 ppm/°C (max) |
| Output Current (source/sink) | 10 mA |
| Supply Voltage Range | 7.2 V to 40 V |
| Noise (0.1 Hz to 10 Hz) | 4 ppm p-p |
| Wideband Noise | 1.5 µVrms |
| Line Regulation | Nearly immune to input voltage variation |
| Long-Term Stability | Excellent (per datasheet) |
| Rango de temperatura de funcionamiento | 0 °C to +70 °C (C-grade commercial) |
| Encapsulado | 8-pin SOIC (S8) |
| Tipo de montaje | Surface Mount |
| Estado RoHS | Compliant (PBF suffix) |
| Lead-Free (PBF) | Yes |
Configuración de pines de LT1236ACS8-5
| Pin 1 | VIN — Power supply input (7.2 V to 40 V) |
| Pin 2 | NC — Not connected (per datasheet) |
| Pin 3 | NC — Not connected (per datasheet) |
| Pin 4 | GND — Ground reference |
| Pin 5 | TRIM — Output voltage trim pin (use 10 kΩ pot to ground) |
| Pin 6 | NR — Noise reduction pin (bypass with 10 nF to ground for low noise) |
| Pin 7 | VOUT — 5.000 V reference output, 10 mA source/sink |
| Pin 8 | NC — Not connected (per datasheet) |
Aplicaciones típicas
LT1236ACS8-5 es adecuado para 6 aplicacións: 16-/18-bit ADC and DAC Reference Rail, Precision Digital Multimeter (DMM) Calibration Reference, Industrial Process Control and Weigh Scales, Test and Measurement Instrumentation, Precision Voltage Regulator and Power Reference, Sensor Signal Conditioning and Excitation.
16-/18-bit ADC and DAC Reference Rail
The LT1236ACS8-5's 5.000 V ±0.05% output and 5 ppm/°C max drift make it the ideal precision anchor for 16-bit SAR ADCs and 18-bit sigma-delta converters. With 1 LSB at 16 bits equal to only 76 µV, the reference's drift contributes less than one LSB error per degree Celsius - far below the ADC's INL budget. Place a 10 µF low-ESR ceramic bypass within 1 cm of the VOUT pin to preserve noise performance. Compared to a bandgap reference, the buried-Zener architecture delivers lower wideband noise (1.5 µVrms) and better long-term stability, critical for instrumentation that must hold accuracy over years.
Recomendado
Precision Digital Multimeter (DMM) Calibration Reference
Handheld and bench DMMs use the LT1236ACS8-5 as the internal calibration anchor for the 5 V range. The ±0.05% initial accuracy (2.5 mV at 5 V) plus 5 ppm/°C drift supports 6.5-digit DMM absolute measurement without periodic recalibration. The 10 mA source/sink capability lets the reference drive resistor-divider networks and protection buffers simultaneously, while the wide 7.2-40 V supply range simplifies battery-powered handheld designs operating directly from 9 V or 12 V rails. Compared to surface-Zener references, the buried-Zener topology eliminates popcorn noise spikes that would otherwise corrupt low-current measurements below 1 µA.
Recomendado
Industrial Process Control and Weigh Scales
Strain-gauge weigh scales and 4-20 mA process-control loops rely on the LT1236ACS8-5 for the excitation supply of bridge sensors and the reference of 16-/18-bit ADCs. The 4 ppm p-p low-frequency noise (0.1 Hz to 10 Hz) is below the noise floor of typical load-cell amplifiers, so the reference does not appear in the final measurement resolution. With 10 mA source current the LT1236 can drive multiple bridge sensors in parallel, simplifying multi-channel scales. The buried-Zener structure also offers excellent thermal hysteresis, surviving solder reflow without the offset shift that plagues bandgap references.
Recomendado
Test and Measurement Instrumentation
Bench source-measurement units, calibrators and data-acquisition systems use the LT1236ACS8-5 as the system-wide 5 V calibration anchor. Its ±0.05% initial accuracy allows end-of-line calibration with minimal software correction, and 4 ppm p-p noise keeps the reference below the analog front-end's own noise floor. The 7.2-40 V supply range lets the reference run directly from internal ±15 V or 24 V rails without pre-regulation. Designers frequently pair the LT1236 with a precision op-amp buffer like the LT1010 or LTC2050 to provide the high source current demanded by multi-channel scanning systems.
Recomendado
Precision Voltage Regulator and Power Reference
The LT1236ACS8-5 can be paired with a series pass transistor to build a precision 5 V regulator with tighter initial accuracy than any LDO. The 10 mA sink capability lets the reference absorb the base current of an external NPN or PNP pass element, and the 7.2 V minimum supply is compatible with standard 9 V or 12 V wall-adapter rails. Compared to monolithic LDOs like the LT3042 or TPS7A4701, this discrete reference-plus-pass approach avoids LDO noise injection into the load while delivering sub-ppm-class long-term stability over months of continuous operation.
Recomendado
Sensor Signal Conditioning and Excitation
Precision sensors - RTDs, thermocouples, strain gauges and LVDTs - need a stable excitation source, and the LT1236ACS8-5 delivers 5.000 V with <5 ppm/°C drift and 4 ppm p-p noise. The 10 mA source current supports multiple sensors in parallel, while the sink capability enables active bridge balancing without external circuitry. Its excellent thermal hysteresis ensures that the cold-junction compensation in thermocouple systems remains stable across reflow and field temperature cycling, which is critical for medical and aerospace instrumentation.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para LT1236ACS8-5 — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | LT1236AIS8-5 | LT1236ACS8-5#PBF | LT1236ACS8-5#TR | LT1236ACS8-5#TRPBF | LT1236BCS8-5 |
|---|---|---|---|---|---|---|
| Package | SOIC-8 (S8) | SOIC-8 (S8) - same | SOIC-8 (S8) - same | SOIC-8 (S8) - same | SOIC-8 (S8) - same | SOIC-8 (S8) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Output Voltage | 5.000 V | 5.000 V | 5.000 V | 5.000 V | 5.000 V | 5.000 V |
| Initial Accuracy | ±0.05% | ±0.05% | ±0.05% | ±0.05% | ±0.05% | ±0.05% |
| Temperature Grade | C-grade (0°C to +70°C) | I-grade (-40°C to +85°C) | C-grade (0°C to +70°C) | C-grade (0°C to +70°C) | C-grade (0°C to +70°C) | B-grade (0°C to +70°C, tighter drift) |
| Maximum TC | 5 ppm/°C | 5 ppm/°C | 5 ppm/°C | 5 ppm/°C | 5 ppm/°C | 2.5 ppm/°C |
| Supply Range | 7.2 V to 40 V | 7.2 V to 40 V | 7.2 V to 40 V | 7.2 V to 40 V | 7.2 V to 40 V | 7.2 V to 40 V |
| Output Current | 10 mA source/sink | 10 mA source/sink | 10 mA source/sink | 10 mA source/sink | 10 mA source/sink | 10 mA source/sink |
Diferenciadores clave
- Industrial temperature range with identical pinout (frente a LT1236AIS8-5)
- Tighter drift in same package for precision upgrades (frente a LT1236BCS8-5)
- RoHS lead-free compliance via PBF suffix (frente a LT1236ACS8-5#PBF)
Notas de diseño
Apply a minimum 7.2 V supply to VIN; below this threshold the buried-Zener reference falls out of regulation and the output collapses. Use a 0.1 µF X7R ceramic in parallel with a 1 µF to 10 µF bulk capacitor placed within 5 mm of the VIN pin to suppress high-frequency line noise. Do not place any series resistance greater than 1 Ω between the supply and VIN, as the reference is designed to be nearly immune to line variation but not to source-to-ground drops. For battery-powered applications, a low-noise boost regulator providing >7.5 V at 20 mA is the cleanest power topology.
Self-heating from the 1.5 mA typical quiescent current plus load current can cause thermal gradients across the die and induce drift. Estimated: with 0.5 W dissipation at 40 V VIN and no load, junction-to-ambient rise on the SOIC-8 with 1 sq inch of copper is approximately 50 °C/W × 0.5 W = 25 °C rise, so install the reference away from heat sources like power inductors and LDO pass transistors. Use a thermal tie between the GND pin (4) and a copper pour to keep the die isothermal with the surrounding PCB.
Route the NR pin (6) directly to a 10 nF X7R bypass capacitor to ground, with the capacitor within 2 mm of the pin - do not share ground vias with high-current paths. Place the VOUT capacitor (10 µF low-ESR ceramic) within 1 cm of the output pin to maintain stability and minimize noise pickup on the reference rail. The NC pins (2, 3, 8) should be tied to GND for mechanical robustness or left floating per the datasheet; floating NC reduces leakage paths. Keep the analog ground separate from digital ground and join only at the reference GND pin to avoid digital switching currents corrupting the reference.
Información de cumplimiento
RoHS/REACH compliance applies to the #PBF (lead-free) suffix per Analog Devices product page; non-PBF lead-finish variants are obsolete. Not AEC-Q100 qualified - automotive designs should use AEC-Q100 qualified references or perform PPAP separately.
