LTC2260IUJ-12 - 12-Bit 105Msps 1.8V ADC | Analog Devices
N.º de pieza: LTC2260IUJ-12 ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.8 | $168,00 |
| 100 | $14.95 | $1.495,00 |
| 500 | $13.2 | $6.600,00 |
| 1.000 | $11.75 | $11.750,00 |
LTC2260IUJ-12 Descripción general
What is a pipelined ADC? A pipelined ADC is a multi-stage analog-to-digital converter architecture that processes the input sample through cascaded low-resolution flash stages, achieving high sampling rates while keeping per-stage complexity manageable. Within the broader signal-chain taxonomy, the LTC2260IUJ-12 belongs to the family of high-speed, low-power SAR/pipeline converters used between the analog front end and a digital signal processor, FPGA, or ASIC. Pipelined ADCs sit alongside successive-approximation (SAR) and flash ADCs as the dominant architectures for sampling rates from a few Msps to several hundred Msps.
Key features of the LTC2260IUJ-12 include single 1.8V supply operation, selectable CMOS, double-data-rate CMOS, or double-data-rate LVDS outputs, an 800 MHz full-power sample-and-hold bandwidth, and a separate output supply that allows the CMOS swing to range from 1.2 V to 1.8 V. Optional features include a data output randomizer, clock duty cycle stabilizer, shutdown and nap modes, and an SPI serial port for configuration. The #PBF suffix indicates a lead-free, RoHS-compliant finish.
The LTC2260IUJ-12 is pin-compatible with the 14-bit LTC2260-14 and 12-bit LTC2261-12/LTC2259-12 siblings in the same 40-QFN footprint, simplifying board reuse when system requirements change resolution or sample rate. The pipelined architecture combined with internal reference and selectable clock options reduces external component count and eases timing closure with downstream FPGAs.
Typical applications include high-bandwidth communications receivers, portable instrumentation, digital oscilloscopes, ultrasound imaging front-ends, and software-defined radio digitizers where low power consumption and high spurious-free dynamic range are required.
When designing the analog input network, ensure the input is AC-coupled or DC-biased within the selected full-scale input range, and route the encode clock with controlled impedance to preserve aperture jitter performance. Use the optional LVDS mode when interfacing to modern FPGAs with LVDS-capable deserialization blocks to minimize switching noise on the digital supply rail.
Alternativas directas para LTC2260IUJ-12 — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con LTC2260IUJ-12 (mismo factor de forma y huella) — difiere en Package, RoHS Status, Operating Temperature, Output Interface, Power Dissipation.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
LTC2260CUJ-12#PBF
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
LTC2260IUJ-14#PBF
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
LTC2261IUJ-12#PBF
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
LTC2259IUJ-12#PBF
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
LTC2258IUJ-14
✅ Sustitución directa✓ En stock
$15.05 / unidad
Ver hoja de datos →LTC2260IUJ-12 Valores máximos y características eléctricas
| Resolución | 12 bits |
| Sample Rate | 105 Msps |
| Number of Input Channels | 1 |
| Architecture | Pipelined |
| Supply Voltage (Analog) | 1.8 V (single) |
| Output Supply Voltage Range | 1.2 V to 1.8 V |
| Power Dissipation | 124 mW at 105 Msps |
| INL (Typical) | ±0.3 LSB |
| DNL (Typical) | ±0.1 LSB |
| Transition Noise | 0.3 LSBRMS |
| Input Range (Selectable) | 1 Vp-p to 2 Vp-p |
| Full-Power Bandwidth | 800 MHz |
| Output Interface | CMOS, DDR CMOS, or DDR LVDS |
| Sample/Hold | Optional S/H |
| Encapsulado | 40-QFN (6 mm x 6 mm) |
| Operating Temperature Range (I grade) | -40C to +85C |
| Configuration Interface | Serial SPI port |
| Shutdown/Nap Modes | Yes |
| Data Output Randomizer | Optional |
| Clock Duty Cycle Stabilizer | Optional |
| Estado RoHS | Compliant (#PBF suffix) |
Configuración de pines de LTC2260IUJ-12
| Pin 1 | AIN+ — Differential analog input (positive) |
| Pin 2 | AIN- — Differential analog input (negative) |
| Pin 3 | REF — Reference voltage decoupling pin |
| Pin 4 | GND — Analog ground |
| Pin 5 | GND — Analog ground |
| Pin 6 | AVDD — Analog 1.8 V supply |
| Pin 7 | GND — Analog ground |
| Pin 8 | GND — Analog ground |
| Pin 9 | ENC+ — Encode clock input (positive) |
| Pin 10 | ENC- — Encode clock input (negative/complementary) |
| Pin 11 | GND — Digital ground |
| Pin 12 | OVDD — Output supply voltage (1.2 V to 1.8 V) |
| Pin 13 | OGND — Output driver ground |
| Pin 14 | D11 — Data output bit 11 (MSB in 12-bit mode) |
| Pin 15 | D10 — Data output bit 10 |
| Pin 16 | D9 — Data output bit 9 |
| Pin 17 | D8 — Data output bit 8 |
| Pin 18 | D7 — Data output bit 7 |
| Pin 19 | D6 — Data output bit 6 |
| Pin 20 | D5 — Data output bit 5 |
| Pin 21 | D4 — Data output bit 4 |
| Pin 22 | D3 — Data output bit 3 |
| Pin 23 | D2 — Data output bit 2 |
| Pin 24 | D1 — Data output bit 1 |
| Pin 25 | D0 — Data output bit 0 (LSB) |
| Pin 26 | DRR/NC — Data ready / not used in single-channel mode |
| Pin 27 | GND — Digital ground |
| Pin 28 | CS — SPI chip select (active low) |
| Pin 29 | SCK — SPI serial clock |
| Pin 30 | SDI — SPI serial data input |
| Pin 31 | SDO — SPI serial data output |
| Pin 32 | GND — Analog ground |
| Pin 33 | SHDN — Shutdown pin (active low) |
| Pin 34 | NAP — Nap mode pin (active low) |
| Pin 35 | MODE — Output mode select (CMOS/DDR/LVDS) |
| Pin 36 | DCS — Duty cycle stabilizer enable |
| Pin 37 | RAND — Output randomizer enable |
| Pin 38 | GND — Analog ground |
| Pin 39 | GND — Analog ground (thermal pad connection) |
| Pin 40 | GND — Exposed pad / analog ground |
Aplicaciones típicas
LTC2260IUJ-12 es adecuado para 6 aplicacións: Software-Defined Radio Digitizer, Portable Digital Oscilloscope, Medical Ultrasound Imaging Front-End, Communications Receiver IF Sampling, Industrial Test and Measurement Instrumentation, Radar and Lidar Signal Acquisition.
Software-Defined Radio Digitizer
The LTC2260IUJ-12's 105 Msps sample rate and 800 MHz full-power analog input bandwidth directly suit the IF/baseband sampling requirement of software-defined radio receivers, where the ADC digitizes a wideband IF segment into an FPGA for channelization. The DDR LVDS output mode minimizes pin count and switching noise coupling into the analog supply, while the 0.3 LSBRMS transition noise preserves signal-to-noise ratio for demodulation of weak signals. At 124 mW from a single 1.8 V supply the LTC2260IUJ-12 fits portable SDR form factors where battery life is critical.
Recomendado
Portable Digital Oscilloscope
The 105 Msps real-time sample rate of the LTC2260IUJ-12, combined with ±0.3 LSB INL linearity and DDR LVDS or CMOS output flexibility, makes it a strong front-end ADC for handheld and bench-top oscilloscopes targeting 30 to 50 MHz analog bandwidth. The 1.8 V single-supply operation simplifies power-rail design for battery-powered instruments, while selectable 1 Vp-p to 2 Vp-p input ranges allow front-end attenuator switching without changing the ADC. Per the Analog Devices datasheet the optional clock duty cycle stabilizer relaxes timing-margin requirements for the FPGA capture memory.
Recomendado
Medical Ultrasound Imaging Front-End
The LTC2260IUJ-12's 124 mW dissipation, 40-QFN small footprint, and 12-bit dynamic range fit ultrasound beamformer receive-channel ADC blocks where many channels share a common board area. The sample rate of 105 Msps supports typical 30 to 40 MHz RF transducer center frequencies after matched filtering, while LVDS output mode keeps board-level EMI under control across dense multi-channel arrays. According to the Analog Devices product family page, the pin-compatible 14-bit LTC2260-14 allows designers to standardize the PCB for mixed-tier ultrasound system product lines.
Recomendado
Communications Receiver IF Sampling
Direct IF sampling to 105 Msps with 12-bit resolution lets the LTC2260IUJ-12 digitize 21 MHz IF strips common in cellular base-station receivers, eliminating analog downconversion to baseband. The 72 dB SNR class ADC combined with selectable full-scale input from 1 Vp-p to 2 Vp-p and SPI gain trim enables wide dynamic-range AGC chains. The DDR LVDS output reduces the FPGA pin count for multi-channel receiver cards, while the 1.8 V supply integrates cleanly into the platform power tree.
Recomendado
Industrial Test and Measurement Instrumentation
Spectrum analyzers, arbitrary waveform digitizers, and power-quality recorders benefit from the LTC2260IUJ-12's 800 MHz full-power bandwidth and low transition noise of 0.3 LSBRMS, which translates directly into cleaner FFT spectra and lower noise floor in vibration analysis. The pin-compatible family scaling to 14-bit resolution lets a single PCB design support multiple instrument tiers. The SPI port allows in-system linearity and gain calibration without hardware rework, and shutdown/nap modes cut power draw in battery-powered field instruments.
Recomendado
Radar and Lidar Signal Acquisition
Pulsed radar baseband and lidar receiver chains use the LTC2260IUJ-12 to capture returns at 105 Msps with 12-bit fidelity. The DDR LVDS mode minimizes digital switching transients coupling into the analog signal path, and the 1.8 V low-power dissipation aids thermal management in sealed outdoor enclosures. Selectable full-scale input ranges via SPI allow real-time AGC adaptation to scene reflectivity without external attenuator switching. The pin-compatible 14-bit LTC2260 family member permits a single PCB platform covering both legacy 12-bit and new 14-bit product SKUs.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para LTC2260IUJ-12 — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | LTC2260CUJ-12#PBF | LTC2260IUJ-14#PBF | LTC2261IUJ-12#PBF | LTC2259IUJ-12#PBF | LTC2258IUJ-14 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Resolution | 12 bits | 12 bits | 14 bits | 12 bits | 12 bits | 14 bits |
| Sample Rate | 105 Msps | 105 Msps | 105 Msps | 80 Msps | 65 Msps | 65 Msps |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Power Dissipation | 124 mW | 124 mW | 147 mW | 103 mW | 87 mW | 87 mW |
| Temperature Grade | Industrial -40C to +85C | Commercial 0C to +70C | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C |
| Output Interface | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS |
| Pin-to-Pin Compatible | Reference | Yes (same 40-QFN) | Yes (same 40-QFN) | Yes (same 40-QFN) | Yes (same 40-QFN) | Yes (same 40-QFN family) |
Diferenciadores clave
- Lowest power in 105 Msps 12-bit ADC class at 124 mW (frente a LTC2204IUK (older 16-bit, 40 Msps ADC))
- Pin-compatible 12-bit/14-bit dual product family in 40-QFN (frente a LTC2260IUJ-14 (14-bit sibling))
- DDR LVDS output mode at 105 Msps reduces FPGA pin count (frente a Older parallel-CMOS-only ADCs like ADS8401 family)
Notas de diseño
The LTC2260IUJ-12 analog input pins (AIN+, AIN-) are highly sensitive to layout parasitics, so the recommended analog input network should be placed within 5 mm of the IC with a symmetric differential trace pair matched to 100 ohms differential. Use a continuous ground plane beneath the analog input traces and isolate them from noisy digital outputs by routing on a different layer or using a ground moat. The exposed thermal pad of the 40-QFN must be soldered to a 6x6 mm copper pour with a minimum of 4 thermal vias to the ground plane for stable operation.
If using the LVDS output mode, route the differential data pairs with 100 ohms differential impedance and length-match within 1 mm across the DDR pairs to maintain timing margin at 105 Msps. The encode clock (ENC+/ENC-) trace should be routed with controlled impedance of 50 ohms per side or 100 ohms differential, and the clock signal should be kept away from data output traces to avoid coupling. Enable the optional clock duty cycle stabilizer (DCS) via SPI when the external clock generator has poor duty cycle, which can otherwise degrade SNR by up to 3 dB at 105 Msps.
Decouple the AVDD pin with a 1 uF ceramic capacitor in parallel with a 0.1 uF high-frequency bypass, both placed within 2 mm of the pin. The OVDD output supply is independent and should also be decoupled near the package with similar capacitance; do not share analog and digital ground returns under the IC - use a star-ground topology or split planes joined at the IC. Estimated: total worst-case supply current is approximately 70 mA from AVDD at full sample rate, so the PCB power plane should be sized accordingly.
Do not leave the SHDN and NAP pins floating - tie SHDN high (logic 1) for normal operation and NAP high unless the system uses nap mode, because floating inputs can cause erratic shutdown cycling. Use the SPI configuration register to enable full 12-bit mode rather than leaving the part in test/reset default mode; verify the resolution by reading back the mode register. Do not apply an analog input that exceeds the selected 1 Vp-p or 2 Vp-p range, or the input ESD protection diodes will forward-bias and degrade linearity permanently.
Información de cumplimiento
Lead-free, RoHS-compliant #PBF suffix. Industrial temperature grade -40C to +85C is standard for the IUJ suffix. AEC-Q100 not applicable for this non-automotive-grade ADC; automotive-grade qualification is not listed by Analog Devices for this part number.
