LTC2287CUP - Dual 10-Bit 40Msps Low Noise 3V ADC | Analog Devices
N.º de pieza: LTC2287CUP ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $13.05 | $13,05 |
| 10 | $11.75 | $117,50 |
| 100 | $10.4 | $1.040,00 |
| 500 | $9.2 | $4.600,00 |
| 1.000 | $8.1 | $8.100,00 |
| 3.000 | $7.05 | $21.150,00 |
LTC2287CUP Descripción general
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples a continuous-time analog voltage and produces a discrete-time digital code representing the input level. Pipelined ADCs use a cascade of low-resolution stages with inter-stage residue amplifiers to achieve high sample rates at moderate power, and dual-channel variants like the LTC2287CUP share a common reference and clock network to guarantee tight gain and offset matching between channels - critical for I/Q baseband, diversity receivers, and medical beamforming.
Key specifications include 3V single-supply operation (2.85V to 3.4V), 235 mW total power dissipation at 40 Msps, 110 dB channel-to-channel isolation at 100 MHz, and selectable multiplexed or simultaneous-sampling operation. The differential inputs accept 1 Vp-p full-scale swings, and the parallel CMOS outputs are easily routed to FPGAs or DSPs with 3V LVCMOS logic. Optional duty-cycle stabiliser and internal reference are factory-trimmed to remove external component count.
The pipelined architecture provides 1.5 clock-cycle latency and supports a 1 to 40 Msps sample-rate window via the CLOCK duty-cycle control pin. Independent shutdown pins reduce per-channel power in time-division applications, and the 64-lead QFN exposed-pad package delivers the thermal performance required for full-rate operation across the 0C to 70C commercial temperature range without derating.
Typical applications include cellular base-station receivers, ultrasound imaging front ends, multi-carrier software-defined radio (SDR) platforms, low-cost oscilloscope channels, and instrumentation digitiser cards. Designers choose the LTC2287CUP when dual-channel 10-bit precision at 40 Msps is needed in a compact, low-power footprint.
For best results, route differential analog inputs as 50 ohm controlled-impedance pairs and place 0.1 uF bypass capacitors adjacent to each supply pin. Confirm that the FPGA timing budget accommodates the 1.5-cycle pipeline latency and that the digital outputs are not loaded above 10 pF per pin to preserve SNR.
This page synthesises distributor pricing, pin-compatible alternatives in the same 64-QFN footprint, and practical design notes not found in the standalone manufacturer datasheet, helping engineers shorten the selection cycle.
Alternativas directas para LTC2287CUP — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con LTC2287CUP (mismo factor de forma y huella) — difiere en Package, SNR, Input Type, RoHS Status, Resolution.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
LTC2287IUP
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
LTC2287CUP#PBF
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
LTC2289CUP
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
LTC2227IUH
✅ Sustitución directa ⚠️ Especificaciones sin verificar✓ En stock
$9.05 / unidad
Ver hoja de datos →LTC2241IUP-12
✅ Sustitución directa ⚠️ Especificaciones sin verificar✓ En stock
$34.5 / unidad
Ver hoja de datos →LTC2287CUP Valores máximos y características eléctricas
| Resolución | 10 bit |
| Number of Channels | 2 (dual) |
| Sample Rate | 40 Msps |
| Input Type | Differential, single-ended optional |
| Tensión de alimentación | 3 V (2.85 V to 3.4 V) |
| Power Dissipation | 235 mW at 40 Msps |
| SNR | 61.6 dB at 70 MHz input |
| SFDR | 85 dB at 70 MHz input |
| Channel Isolation | 110 dB at 100 MHz |
| Output Interface | Parallel CMOS |
| Architecture | Pipelined |
| Input Range | 1 Vp-p differential full-scale |
| Temperatura de funcionamiento | 0 C to 70 C (commercial grade) |
| Encapsulado | 64-pin QFN (9x9 mm) with exposed pad |
| Tipo de montaje | Surface Mount |
| Nivel MSL | 1 |
| Estado RoHS | Compliant |
Configuración de pines de LTC2287CUP
| Pin 1 | INA+ — Channel A positive differential analog input |
| Pin 2 | INA- — Channel A negative differential analog input |
| Pin 3 | VCM_A — Channel A common-mode voltage |
| Pin 4 | REFA — Channel A reference decoupling |
| Pin 5 | VA — Analog 3V supply |
| Pin 6 | GND — Analog ground |
| Pin 7 | VA — Analog 3V supply |
| Pin 8 | GND — Analog ground |
| Pin 9 | VREF — Internal reference decoupling |
| Pin 10 | SENSE — Reference voltage sense pin |
| Pin 11 | GND — Analog ground |
| Pin 12 | VA — Analog 3V supply |
| Pin 13 | INB- — Channel B negative differential analog input |
| Pin 14 | INB+ — Channel B positive differential analog input |
| Pin 15 | VCM_B — Channel B common-mode voltage |
| Pin 16 | REFB — Channel B reference decoupling |
| Pin 17 | GND — Analog ground |
| Pin 18 | GND — Analog ground |
| Pin 19 | ENC+ — Clock input positive |
| Pin 20 | ENC- — Clock input negative |
| Pin 21 | GND — Digital ground |
| Pin 22 | VD — Digital 3V supply |
| Pin 23 | GND — Digital ground |
| Pin 24 | SHDA — Channel A shutdown (active low) |
| Pin 25 | SHDB — Channel B shutdown (active low) |
| Pin 26 | MUX — Multiplexed mode select |
| Pin 27 | DCS — Duty cycle stabiliser enable |
| Pin 28 | OGND — Output driver ground |
| Pin 29 | OVD — Output driver 3V supply |
| Pin 30 | DB0 — Digital output bit 0 (LSB) |
| Pin 31 | DB1 — Digital output bit 1 |
| Pin 32 | DB2 — Digital output bit 2 |
| Pin 33 | DB3 — Digital output bit 3 |
| Pin 34 | DB4 — Digital output bit 4 |
| Pin 35 | DB5 — Digital output bit 5 |
| Pin 36 | DB6 — Digital output bit 6 |
| Pin 37 | DB7 — Digital output bit 7 |
| Pin 38 | DB8 — Digital output bit 8 |
| Pin 39 | DB9 — Digital output bit 9 (MSB) |
| Pin 40 | OF_A — Channel A over-range flag |
| Pin 41 | OF_B — Channel B over-range flag |
| Pin 42 | CLKOUT — Clock output for data synchronisation |
| Pin 43 | GND — Digital ground |
| Pin 44 | VD — Digital 3V supply |
| Pin 45 | GND — Digital ground |
| Pin 46 | D9A — Channel A digital output bit 9 |
| Pin 47 | D8A — Channel A digital output bit 8 |
| Pin 48 | D7A — Channel A digital output bit 7 |
| Pin 49 | D6A — Channel A digital output bit 6 |
| Pin 50 | D5A — Channel A digital output bit 5 |
| Pin 51 | D4A — Channel A digital output bit 4 |
| Pin 52 | D3A — Channel A digital output bit 3 |
| Pin 53 | D2A — Channel A digital output bit 2 |
| Pin 54 | D1A — Channel A digital output bit 1 |
| Pin 55 | D0A — Channel A digital output bit 0 |
| Pin 56 | OFA — Channel A overflow indicator |
| Pin 57 | OFB — Channel B overflow indicator |
| Pin 58 | D0B — Channel B digital output bit 0 |
| Pin 59 | D1B — Channel B digital output bit 1 |
| Pin 60 | D2B — Channel B digital output bit 2 |
| Pin 61 | D3B — Channel B digital output bit 3 |
| Pin 62 | D4B — Channel B digital output bit 4 |
| Pin 63 | D5B — Channel B digital output bit 5 |
| Pin 64 | PAD — Exposed thermal pad - tie to ground |
Aplicaciones típicas
LTC2287CUP es adecuado para 6 aplicacións: Cellular Base-Station Receiver, Ultrasound Imaging Front End, Multi-Carrier Software-Defined Radio, Low-Cost Oscilloscope Channel, Instrumentation Digitiser Card, Radar and Lidar IF Sampling.
Cellular Base-Station Receiver
The LTC2287CUP's dual 10-bit 40 Msps channels and 110 dB channel isolation make it well matched to multi-carrier base-station receiver IF chains. Each channel digitises one I or Q branch of the IF downconverted signal at 61.6 dB SNR, while high channel-to-channel isolation prevents cross-talk that would otherwise corrupt image rejection. The 235 mW power budget at 3V supply keeps the ADC below 2% of typical RRH board power. Differential inputs accept the 1 Vp-p swing from a front-end IF amplifier, and the parallel CMOS outputs feed directly into a baseband FPGA or DSP without external bus buffers. Designers choose this ADC over flash or SAR parts because pipelined architecture guarantees continuous 40 Msps sampling without throughput gaps.
Recomendado
Ultrasound Imaging Front End
In ultrasound beamforming arrays the LTC2287CUP provides tightly matched dual-channel sampling of transducer element pairs. The 110 dB isolation keeps adjacent-element leakage below the noise floor required for sub-millimetre resolution, and the simultaneous-sampling mode eliminates inter-channel skew. The 40 Msps sample rate covers typical 1-15 MHz transducer bandwidth after anti-alias filtering, with 61.6 dB SNR preserving dynamic range for harmonic-imaging modes. Power dissipation of 235 mW across two channels lets designers stack 16 to 32 ADC devices per board without exceeding thermal budgets; the exposed-pad 64-QFN package spreads heat evenly across the ground pour.
Recomendado
Multi-Carrier Software-Defined Radio
SDR platforms digitising two simultaneous RF bands benefit from the LTC2287CUP's dual simultaneous-sampling architecture. The 40 Msps aggregate rate (80 Msps multiplexed) accommodates 4G LTE and 5G NR sub-6 GHz signals after quadrature downconversion, and the 85 dB SFDR keeps spurs below the in-band blocker mask. A single 3V supply rails simplifies LDO selection, while the parallel CMOS output bus maps cleanly to FPGA LVCMOS banks. Designers often pair the LTC2287CUP with the AD9864 mixed-signal front end or the AD9361 transceiver for complete SDR channel cards.
Recomendado
Low-Cost Oscilloscope Channel
The LTC2287CUP supports cost-optimised 100 MHz class oscilloscope channels when dual ADCs are used per channel for interleaved sampling or two-channel capture. Its 61.6 dB SNR and 85 dB SFDR match the ENOB of a 10-bit scope frontend, and the pipelined 1.5-cycle latency is acceptable for triggered acquisitions. Differential inputs tolerate the DC-restored attenuator outputs, and the 235 mW power figure allows battery-powered handheld scopes. Designers often pair it with an FPGA that performs trigger logic, channel-to-channel skew correction, and peak-detect display processing.
Recomendado
Instrumentation Digitiser Card
Modular data-acquisition cards in PXI and LXI instruments deploy the LTC2287CUP for simultaneous two-channel digitisation of strain gauges, vibration sensors, and process-control loops. The dual 40 Msps channels handle 10 MHz bandwidth sensor outputs, while the 110 dB isolation prevents motor-coupled noise from contaminating adjacent measurement channels. A 3V single-supply rail eases compliance with industrial EMC immunity standards. The exposed-pad 64-QFN footprint ensures uniform thermal performance across densely populated multi-card chassis.
Recomendado
Radar and Lidar IF Sampling
The LTC2287CUP dual 10-bit 40 Msps performance fits automotive radar and lidar IF stages where matched pairs of baseband outputs require simultaneous sampling. The 85 dB SFDR avoids spur false-target returns in FMCW radar processing, and the differential inputs are directly compatible with common IF amplifier outputs like the ADL5201. Power at 235 mW fits within space-constrained automotive sensor heads, and the 64-QFN package enables compact PCB placement near the antenna feed network. Designers validate thermal headroom for automotive grade by selecting the LTC2287IUP variant.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para LTC2287CUP — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | LTC2287IUP | LTC2287CUP#PBF | LTC2289CUP | LTC2227IUH | LTC2241IUP-12 |
|---|---|---|---|---|---|---|
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 32-QFN - different | 64-QFN (9x9 mm) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 12 bit | 12 bit |
| Sample Rate | 40 Msps | 40 Msps | 40 Msps | 65 Msps | 40 Msps | 40 Msps |
| Number of Channels | 2 | 2 | 2 | 2 | 1 | 1 |
| SNR at 70 MHz | 61.6 dB | 61.6 dB | 61.6 dB | 61.4 dB | 65.5 dB | 65.5 dB |
| Power Dissipation | 235 mW | 235 mW | 235 mW | 400 mW | 120 mW | 120 mW |
| Operating Temperature | 0 C to 70 C | -40 C to 85 C | 0 C to 70 C | 0 C to 70 C | -40 C to 85 C | -40 C to 85 C |
Diferenciadores clave
- Industry-leading 110 dB channel-to-channel isolation (frente a LTC2289CUP)
- Lowest power dissipation in dual 10-bit 40 Msps class (frente a LTC2289CUP)
- Flexible multiplexed or simultaneous-sampling operation (frente a ADS8401IPFBR)
Notas de diseño
Route the differential analog inputs as 50 ohm controlled-impedance pairs with continuous ground reference on the layer beneath. Place 0.1 uF ceramic bypass capacitors adjacent to every VA and VD supply pin, plus a single 10 uF tantalum or ceramic bulk capacitor near the device. The exposed thermal pad must be soldered to a continuous ground plane with at least 16 thermal vias for 235 mW dissipation; insufficient ground stitching raises junction temperature and degrades SNR. According to Analog Devices evaluation-kit guidelines, keep digital output traces short and away from analog inputs to avoid digital-noise coupling into the analog front end.
Use an external clock driver such as the AD9517-4 or AD9520-3 with jitter below 1 ps rms to preserve the 61.6 dB SNR budget at 40 Msps. The LTC2287CUP accepts a differential PECL/LVDS clock at the ENC+/ENC- pins; single-ended drive is possible but reduces SNR by 1-2 dB. According to the datasheet, the duty-cycle stabiliser pin (DCS) should be enabled when the clock duty cycle is not exactly 50%, since 1% clock skew translates to a measurable SNR penalty at full Nyquist input. Estimate: jitter-limited SNR (dB) = 20*log10(1/(2*pi*fin*tj)) where fin is the analog input frequency and tj is the total integrated jitter.
The 235 mW dissipation at 40 Msps comes primarily from the analog front end and reference buffer; at sample rates below 20 Msps the LTC2287CUP power scales down roughly linearly. Use the per-channel SHDA and SHDB pins to power-gate unused channels, dropping quiescent draw by approximately 50 mW per channel. According to the Analog Devices datasheet, the VA and VD rails may share a single 3V LDO with adequate decoupling, but for best SNR a ferrite-bead-isolated analog LDO (e.g. ADP7118) feeding VA is recommended. Estimated: total quiescent with both channels enabled equals roughly 50 mA at 3V.
Do not drive the CMOS outputs with more than 10 pF per pin; excessive capacitive load slows edge rates and degrades setup/hold margins at the FPGA. Confirm the input common-mode voltage matches the VCM_A/VCM_B internal bias (typically 1.5V at 3V supply) - leaving inputs floating injects switching noise into the substrate. According to Analog Devices datasheet guidance, the SENSE pin must be tied to VREF for internal reference operation; leaving it open disables the reference and produces erratic output codes. Finally, ensure the differential clock amplitude at ENC+/ENC- is at least 400 mVp-p to avoid metastable sampling.
Información de cumplimiento
RoHS compliant per Analog Devices product page. Lead-free finish confirmed by #PBF suffix. AEC-Q100 not qualified - choose industrial-temperature LTC2287IUP for non-automotive extended-temperature designs.
