MAX122ACAG - 12-Bit 333ksps SAR ADC, 24-SSOP | Maxim Integrated
N.º de pieza: MAX122ACAG ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $32.16 | $32,16 |
| 10 | $29.5 | $295,00 |
| 100 | $25.8 | $2.580,00 |
| 500 | $22.4 | $11.200,00 |
| 1.000 | $19.95 | $19.950,00 |
MAX122ACAG Descripción general
A SAR ADC is a type of ADC that performs a binary-search conversion cycle against an internal capacitive DAC, yielding deterministic latency (one conversion clock per N bits) and zero pipeline delay. SAR converters sit in the broader hierarchy of analog-to-digital converters, which includes flash, pipeline, delta-sigma, and dual-slope architectures. SAR parts are favored when the application needs a single-shot, low-latency snapshot of an analog waveform rather than the high oversampling of a sigma-delta or the wide bandwidth of a flash ADC. The MAX122 family, in particular, balances speed, accuracy, and integration for instrumentation, control loops, and DSP front-ends.
Key specifications include 12-bit resolution, a 333 ksps sampling rate, an internal track/hold with sub-microsecond acquisition, an integrated buried-zener-like reference, and a parallel digital interface. The BiCMOS process allows low analog supply current while supporting TTL/CMOS-compatible parallel logic. Input ranges are typically 0V to +5V unipolar or ±5V bipolar when driven through appropriate signal conditioning, and the parallel output format simplifies connection to standard digital ASICs or DSPs without a serial-port overhead.
The MAX122ACAG is typically used in high-speed data-acquisition cards, industrial control systems, digital signal processing front-ends, multiplexed data-logging systems, and precision instrumentation. The device's 500 ksps internal conversion capability (some family members ship rated at 333 ksps or 500 ksps depending on temperature grade) and the on-chip 2.5V reference make it attractive where board area and component count are constrained.
When designing with this ADC, pay close attention to analog input drive amplifiers - a fast-settling op amp is required so the input settles within the acquisition window. Decouple the AVdd pin with both a 10 uF bulk and a 0.1 uF ceramic capacitor placed within 5 mm of the pin to keep reference noise out of the conversion. Use a single-point ground for the AGND pin to avoid digital return currents contaminating the analog ground.
This page synthesizes distributor pricing, drop-in alternatives in the same 24-SSOP footprint, and practical design notes not found in a single manufacturer datasheet.
Alternativas directas para MAX122ACAG — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
MAX122ACAG+
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
MAX122BCAG+
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
MAX122AEAG+
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
MAX122BCAG
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
MAX122ACAG Valores máximos y características eléctricas
| Resolución | 12 bits |
| Frecuencia de muestreo | 333 ksps |
| Number of Channels | 1 |
| Architecture | SAR (Successive Approximation) |
| Input Type | Single-Ended (with T/H) |
| Data Interface | Parallel |
| Encapsulado | 24-SSOP (0.209 inch / 5.30 mm width) |
| Número de pines | 24 |
| Tipo de montaje | Surface Mount (Gull Wing) |
| Reference | Internal (integrated low-drift voltage reference) |
| Track-and-Hold | Integrated (on-chip) |
| Technology | BiCMOS |
Configuración de pines de MAX122ACAG
| Pin 1 | VSS — Negative supply / analog ground return |
| Pin 2 | AGND — Analog ground |
| Pin 3 | AIN — Analog input |
| Pin 4 | REFADJ — Reference adjust / reference bypass |
| Pin 5 | REF — 2.5V internal reference output |
| Pin 6 | DGND — Digital ground |
| Pin 7 | AVDD — +5V analog supply |
| Pin 8 | DVDD — +5V digital supply |
| Pin 9 | CS — Active-low chip select |
| Pin 10 | RD — Active-low read strobe |
| Pin 11 | WR/RDY — Write / conversion start |
| Pin 12 | D0/D8 — Data bit 0 (parallel mode bit-mapped) |
| Pin 13 | D1/D9 — Data bit 1 |
| Pin 14 | D2/D10 — Data bit 2 |
| Pin 15 | D3/D11 — Data bit 3 |
| Pin 16 | D4 — Data bit 4 |
| Pin 17 | D5 — Data bit 5 |
| Pin 18 | D6 — Data bit 6 |
| Pin 19 | D7 — Data bit 7 (MSB in byte mode) |
| Pin 20 | CLK — External conversion clock input |
| Pin 21 | EOC — End-of-conversion output (active low) |
| Pin 22 | MODE — Parallel mode select |
| Pin 23 | HBEN — High-byte enable (byte-mode) |
| Pin 24 | VDD — Positive supply (alias for AVDD on some revisions) |
Aplicaciones típicas
MAX122ACAG es adecuado para 6 aplicacións: High-Speed Data Acquisition Cards, Industrial Process Control Loops, DSP Front-End Signal Conditioning, Multiplexed Data Logging Systems, Precision Instrumentation, Motor Control Position Feedback.
High-Speed Data Acquisition Cards
The MAX122ACAG's 333 ksps sampling rate and 12-bit resolution make it a strong fit for multi-channel data-acquisition cards where a multiplexer feeds one shared ADC. Its integrated track-and-hold acquires the analog input within the converter's acquisition window, eliminating the need for an external sample-and-hold amplifier. The parallel 12-bit output simplifies connection to FPGAs or microcontrollers that time-multiplex conversion results into system memory. The single +5V supply and integrated 2.5V reference reduce board-area constraints versus discrete ADC front-ends.
Recomendado
Industrial Process Control Loops
The MAX122ACAG's SAR architecture delivers deterministic single-shot conversion latency - one conversion clock per 12 bits, with no pipeline delay - which is critical for closed-loop process control where every microsecond of delay affects loop stability. The 0C/+70C commercial temperature range of the ACAG (or the -40C/+85C industrial range of the ACAG+) suits factory-floor environments. The integrated low-drift internal voltage reference stabilizes calibration against temperature drift over months of operation, reducing maintenance recalibration cycles.
Recomendado
DSP Front-End Signal Conditioning
The MAX122ACAG pairs naturally with DSP chips in audio-bandwidth and ultrasonic signal-processing front-ends: a 333 ksps sampling rate covers signal bandwidths up to roughly 150 kHz at the Nyquist limit, and the parallel 12-bit output is read in single instruction cycles by most DSPs. Designers typically precede the ADC with an op-amp gain stage (for example, the MAX4108) and a low-pass anti-aliasing filter. The internal reference and BiCMOS front-end minimize external components in the analog signal chain.
Recomendado
Multiplexed Data Logging Systems
The MAX122ACAG fits multiplexed data-logging systems where a single ADC is shared across many sensor channels: each channel switch settles during the track/hold acquisition phase, then a single conversion captures the value. With 333 ksps, a 16-channel multiplexer can sample each sensor at >20 kHz, sufficient for vibration monitoring or fast thermal profiling. The integrated 2.5V reference eliminates one of the dominant drift sources in low-noise precision loggers.
Recomendado
Precision Instrumentation
The MAX122ACAG supports precision instrumentation such as bench-top multimeters, spectrum analyzer IF digitizers, and scanner/recorder channels. Its 12-bit resolution yields approximately 0.024% full-scale quantization (1 LSB at 5V is ~1.22 mV), adequate for general-purpose instrumentation measurements, and the parallel interface simplifies timing closure in time-critical instruments. Designers typically add a precision front-end op-amp (such as the MAX4108 or MAX4109) to drive the converter to within its rated linearity.
Recomendado
Motor Control Position Feedback
The MAX122ACAG's low single-conversion latency is well suited to motor-control position-feedback loops where a resolver or encoder output drives an analog channel and must be digitized each PWM cycle. The 333 ksps rate supports control-loop rates above 100 kHz with margin for multi-channel multiplexing. The internal reference and small 24-SSOP footprint ease integration onto compact motor-control PCBs, and the integrated track/hold synchronizes the sample instant to the PWM timer.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para MAX122ACAG — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | MAX122ACAG+ | MAX122BCAG+ | MAX122AEAG+ | MAX122BCAG |
|---|---|---|---|---|---|
| Brand | Maxim Integrated (Analog Devices) | Maxim Integrated (Analog Devices) | Maxim Integrated (Analog Devices) | Maxim Integrated (Analog Devices) | Maxim Integrated (Analog Devices) |
| Package | 24-SSOP (5.30 mm) | 24-SSOP (5.30 mm) - same | 24-SSOP (5.30 mm) - same | 24-SSOP (5.30 mm) - same | 24-SSOP (5.30 mm) - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Sampling Rate | 333 ksps | 333 ksps | 500 ksps (+50%) | 333 ksps | 500 ksps (+50%) |
| Number of Channels | 1 | 1 | 1 | 1 | 1 |
| Architecture | SAR | SAR | SAR | SAR | SAR |
| Operating Temperature | 0C to +70C (Commercial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) |
| Internal Reference | Yes (integrated) | Yes (integrated) | Yes (integrated) | Yes (integrated) | Yes (integrated) |
| Track-and-Hold | Integrated | Integrated | Integrated | Integrated | Integrated |
Diferenciadores clave
- Integrated reference and track/hold on BiCMOS die (frente a MAX122ACNG+)
- Commercial-temperature grade at lower cost (frente a MAX122BCAG+)
- Single-supply +5V operation (frente a Discrete ADC front-ends (external ADC + separate reference IC))
Notas de diseño
Place both the 10 uF bulk and 0.1 uF ceramic decoupling capacitors on AVDD and DVDD within 5 mm of their respective pins, with the trace vias placed immediately at the capacitor pads. Use a single-point star ground connecting AGND and DGND at the device to avoid digital return currents contaminating the analog ground reference.
Route the parallel data bus D0-D11 as short as possible and avoid running them parallel to the analog input trace or the CLK signal to minimize crosstalk. Keep the analog input trace guarded by ground pours on both sides and isolate the AGND pin's ground from the digital ground return at the IC, joining only at the power-supply star point.
Do not skip the REF capacitor - the integrated 2.5V reference requires an external bypass capacitor on REF (typically 4.7 uF) for stable operation, otherwise INL/INL errors increase. Ensure the input amplifier can settle within the track-and-hold acquisition window (typically <350 ns) or the converter will sample an unsettled input and degrade effective resolution.
Información de cumplimiento
RoHS and lead-free status not confirmed by the provided web data (heisener listing does not specify). Compliance fields require verification from the official Analog Devices / Maxim Integrated datasheet document before PCB assembly in RoHS-restricted jurisdictions.
