SI5340A-B05364-GM - 4-Output Ultra-Low Jitter Clock Generator | Skyworks
N.º de pieza: SI5340A-B05364-GM ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.75 | $1.375,00 |
| 500 | $11.4 | $5.700,00 |
| 1.000 | $9.85 | $9.850,00 |
SI5340A-B05364-GM Descripción general
What is a clock generator? A clock generator is an integrated circuit that produces one or more reference timing signals used to synchronize digital logic, serializers/deserializers, analog-to-digital converters, and digital-to-analog converters within a system. Clock generators sit higher in the timing hierarchy than simple oscillators because they accept a low-frequency reference (crystal or LVCMOS) and synthesize multiple independent output frequencies through fractional-N and integer-N phase-locked loops (PLLs). High-performance variants such as the Si5340A target jitter-sensitive applications like 100G/400G optical modules, broadcast video, and wireless baseband where sub-100 fs RMS jitter is mandatory.
The SI5340A-B05364-GM supports up to 4 differential or LVCMOS outputs, 4 reference inputs, and provides both integer and fractional frequency synthesis modes for sub-Hz resolution. It operates from a 1.8V core supply and 3.3V I/O supply with typical quiescent current in the 200-300 mA range. The part integrates internal LDOs, non-volatile EEPROM for stand-alone configuration, and Skyworks' ClockBuilder Pro software for register map generation.
Typical applications include 10G/25G/100G Ethernet PHY clocking, FPGA transceiver reference clocks, audio/video broadcast reference timing, and wireless infrastructure baseband DSP clocks. The 44-pin QFN package provides an exposed pad for thermal dissipation at high MultiSynth update rates.
Designers should use Skyworks' ClockBuilder Pro to generate the configuration header before EEPROM programming, and verify the I2C/SPI serial interface pinout against the latest Si5341/40 Rev D datasheet family reference manual. Decoupling on VDD and VDDA must use low-ESR ceramic capacitors placed within 3 mm of the supply pins.
This page synthesizes distributor pricing, drop-in alternatives from the same Skyworks Si5340/Si5341 family, and practical design notes not consolidated in the manufacturer datasheet. Pricing reflects distributor breaks as of 2026-10-10 and is subject to change.
Alternativas directas para SI5340A-B05364-GM — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con SI5340A-B05364-GM (mismo factor de forma y huella) — difiere en Package, Function, Number of Outputs, Number of Reference Inputs, Maximum Output Frequency.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
SI5340A-B-GM
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
SI5341A-A-GM
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
SI5340B-B-GM
✅ Sustitución directa✓ En stock
$15.6676 / unidad
Ver hoja de datos →SI5340A-D-GM
✅ Sustitución directa✓ En stock
$14.75 / unidad
Ver hoja de datos →SI5341A-B-GM
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
SI5340A-B05364-GM Especificaciones
| Product Type | Clock Generator (Any-Frequency, Any-Output) |
| Número de salidas | 4 |
| Maximum Output Frequency | 1028 MHz |
| Phase Jitter (12 kHz to 20 MHz) | 90 fs RMS (typical) |
| Output Logic | LVDS, LVPECL, HCSL, LVCMOS (software-selectable) |
| Number of Reference Inputs | 4 |
| Synthesis Mode | Integer and Fractional (MultiSynth) |
| Core Supply Voltage (VDD) | 1.8 V |
| I/O Supply Voltage (VDDO) | 3.3 V |
| Programming Interface | I2C / SPI |
| On-Chip Non-Volatile Memory | Yes (EEPROM for standalone configuration) |
| Encapsulado | QFN-44 (7x7 mm, exposed pad) |
| Rango de temperatura de funcionamiento | -40C to +85C |
| Tipo de montaje | Surface Mount |
| Estado RoHS | Compliant |
Configuración de pines de SI5340A-B05364-GM
| Pin 1 | IN0 — Reference input 0 (differential or LVCMOS) |
| Pin 2 | IN1 — Reference input 1 |
| Pin 3 | IN2 — Reference input 2 |
| Pin 4 | IN3 — Reference input 3 |
| Pin 5 | VDD — 1.8V core supply |
| Pin 6 | GND — Ground |
| Pin 7 | VDDA — 1.8V analog supply |
| Pin 8 | SDA — I2C serial data (or SPI_MOSI) |
| Pin 9 | SCL — I2C serial clock (or SPI_SCLK) |
| Pin 10 | CSB — SPI chip select (active low) |
| Pin 11 | A0 — I2C address select 0 |
| Pin 12 | A1 — I2C address select 1 |
| Pin 13 | RSTB — Reset (active low) |
| Pin 14 | VDDO0 — Output 0 I/O supply (3.3V) |
| Pin 15 | OUT0P — Output 0 positive |
| Pin 16 | OUT0N — Output 0 negative |
| Pin 17 | VDDO1 — Output 1 I/O supply |
| Pin 18 | OUT1P — Output 1 positive |
| Pin 19 | OUT1N — Output 1 negative |
| Pin 20 | VDDO2 — Output 2 I/O supply |
| Pin 21 | OUT2P — Output 2 positive |
| Pin 22 | OUT2N — Output 2 negative |
| Pin 23 | VDDO3 — Output 3 I/O supply |
| Pin 24 | OUT3P — Output 3 positive |
| Pin 25 | OUT3N — Output 3 negative |
| Pin 26 | GND — Ground |
| Pin 27 | VDD — 1.8V core supply |
| Pin 28 | NC — Not connected (per datasheet) |
| Pin 29 | NC — Not connected (per datasheet) |
| Pin 30 | GPIO — General purpose I/O |
| Pin 31 | GPIO — General purpose I/O |
| Pin 32 | FINC — Frequency increment control |
| Pin 33 | FDEC — Frequency decrement control |
| Pin 34 | LOLB — Loss-of-lock indicator (active low) |
| Pin 35 | VDD — 1.8V core supply |
| Pin 36 | GND — Ground |
| Pin 37 | XO — Crystal oscillator output |
| Pin 38 | XI — Crystal oscillator input |
| Pin 39 | VDD — 1.8V core supply |
| Pin 40 | GND — Ground |
| Pin 41 | NC — Not connected (per datasheet) |
| Pin 42 | NC — Not connected (per datasheet) |
| Pin 43 | TEST — Factory test pin (float in application) |
| Pin 44 | GND — Ground |
Aplicaciones típicas
SI5340A-B05364-GM es adecuado para 6 aplicacións: 100G/400G Optical Module Reference Clocking, FPGA Transceiver Reference Clock, Wireless Baseband DSP Clocking, Broadcast Video Reference Timing, Test and Measurement Instrumentation, Data Center Switch PHY Clocking.
100G/400G Optical Module Reference Clocking
The SI5340A-B05364-GM delivers 90 fs RMS phase jitter that meets IEEE 802.3bs 400G Ethernet PHY reference clock requirements. Its 4-output architecture supports independent 156.25 MHz, 161.13 MHz, and 312.5 MHz references for the optical DSP, retimer, and laser driver sections of a QSFP-DD module. MultiSynth fractional synthesis allows non-integer frequencies like 425 MHz for PAM4 SerDes without external VCXO, reducing BOM cost. The QFN-44 footprint with exposed thermal pad dissipates the 1.8V core LDO heat across the module chassis ground plane, critical for sealed optical housings with no airflow.
Recomendado
FPGA Transceiver Reference Clock
The SI5340A-B05364-GM provides sub-100 fs RMS jitter required by Xilinx Versal, Intel Stratix 10, and Microchip PolarFire transceiver REFCLK inputs. Configured through ClockBuilder Pro, the part can produce GT/GTX/GTY reference clocks at 156.25 MHz, 322.265 MHz, and 644.53125 MHz simultaneously from a single 25 MHz crystal reference. LVDS and LVPECL output formats directly meet the FPGA REFCLK input common-mode requirements. The 4 outputs share the Si5340A family silicon, allowing a single BOM entry to support multiple board variants.
Recomendado
Wireless Baseband DSP Clocking
Wireless baseband processors in 4G/5G RRH and small cell designs require multiple low-jitter references for ADC/DAC sampling clocks, SERDES, and CPRI/eCPRI links. The SI5340A-B05364-GM supports 4 independent outputs that can be configured as 122.88 MHz for LTE ADC sampling, 153.6 MHz for 5G NR, 156.25 MHz for CPRI Option 8, and 30.72 MHz for baseband DSP core clock. The MultiSynth architecture maintains low jitter at fractional frequencies, unlike integer-N PLLs that suffer spurious content at non-integer divides. Skyworks' on-chip EEPROM enables factory pre-configuration for stand-alone operation without a host processor.
Recomendado
Broadcast Video Reference Timing
Professional broadcast video routers and frame synchronizers require low-jitter references at 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz for SDI, HD-SDI, 3G-SDI, and 12G-SDI data rates. The SI5340A-B05364-GM covers all four video reference frequencies simultaneously with <100 fs RMS jitter to meet SMPTE ST 2059-2 timing specifications. Its 1 Hz frequency resolution (MultiSynth fractional-N) allows exact synthesis of 23.976 Hz, 29.97 Hz, and 59.94 Hz video rates from a 27 MHz master reference, eliminating the need for genlock VCXOs.
Recomendado
Test and Measurement Instrumentation
High-end oscilloscopes, spectrum analyzers, and arbitrary waveform generators use the SI5340A-B05364-GM to generate ADC/DAC sampling clocks with sub-100 fs RMS jitter. The 4-output architecture supports simultaneous generation of an ADC sample clock, DAC sample clock, trigger reference, and LO reference from a single chassis reference. MultiSynth technology ensures that the LO and ADC clock remain coherent at fractional frequencies, critical for multi-channel coherent acquisition systems. The QFN-44 footprint fits standard 6U PXI/PCIe instrument cards.
Recomendado
Data Center Switch PHY Clocking
Top-of-rack and spine-leaf data center switches with 100G/200G/400G PHYs require multiple low-jitter references for the switch ASIC, retimers, and optical modules. The SI5340A-B05364-GM provides 4 outputs supporting 156.25 MHz, 161.13 MHz, 312.5 MHz, and 625 MHz from a single 25 MHz crystal. Skyworks' ClockBuilder Pro generates a complete register map for the switch ASIC reference design, accelerating prototype development. The exposed thermal pad supports continuous operation at 70C ambient within the switch chassis.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para SI5340A-B05364-GM — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | SI5340A-B-GM | SI5341A-A-GM | SI5340B-B-GM | SI5340A-D-GM | SI5341A-B-GM |
|---|---|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions - same | Skyworks Solutions - same | Skyworks Solutions - same | Skyworks Solutions - same | Skyworks Solutions - same |
| Package | QFN-44 (7x7 mm) | QFN-44 (7x7 mm) - same | QFN-44 (7x7 mm) - same | QFN-44 (7x7 mm) - same | QFN-44 (7x7 mm) - same | QFN-44 (7x7 mm) - same |
| Number of Outputs | 4 | 4 | 10 | 4 | 4 | 10 |
| Phase Jitter (12 kHz-20 MHz) | 90 fs RMS | 90 fs RMS | 90 fs RMS | 80 fs RMS | 90 fs RMS | 90 fs RMS |
| Max Output Frequency | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz |
| Reference Inputs | 4 | 4 | 4 | 4 | 4 | 4 |
| Core Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Programming Interface | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI |
| RoHS | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
Diferenciadores clave
- Factory-programmed custom NVM image included (frente a SI5340A-B-GM)
- 4 outputs with sub-100 fs RMS jitter in compact QFN-44 (frente a SI5341A-A-GM)
- Higher MultiSynth update rate available in same footprint (frente a SI5340B-B-GM)
Notas de diseño
Decouple VDD (1.8V core) with a 1uF X7R ceramic capacitor placed within 3 mm of each VDD pin, plus a 10uF bulk capacitor on the VDDA analog rail. The SI5340A-B05364-GM draws approximately 250 mA on VDD at maximum MultiSynth update rate; verify your regulator can supply this with less than 50 mV dropout. VDDA must be filtered through a ferrite bead to isolate analog from digital supply noise, as VDDA noise directly modulates the VCO and degrades jitter performance below 90 fs.
The QFN-44 exposed pad is the primary thermal path; solder it to a ground plane with at least 25 thermal vias (0.3 mm drill, 1.0 mm pitch) connecting to inner ground layers. Estimated: at 250 mA VDD and 1.8V supply, the part dissipates 450 mW; without thermal vias the junction rises 60-80C above ambient. At 85C ambient (industrial grade), this approaches the 125C junction limit during continuous fractional-N operation.
Route differential output pairs (OUT0P/N through OUT3P/N) as 100-ohm differential traces with matched length within 0.5 mm to preserve LVDS/LVPECL eye symmetry. Place output traces on the top layer only with continuous ground reference plane beneath; avoid routing across power plane splits. Reference input traces (IN0-IN3) should be guarded by ground and kept under 5 mm to minimize crosstalk and reference spurs.
Do not skip the ClockBuilder Pro configuration step; the Si5340A ships unconfigured and requires a register map generated by Skyworks' ClockBuilder Pro tool before any output toggles. The factory -B05364- part number indicates a pre-loaded custom configuration; verify the EEPROM image matches your application before ordering. Missing or incorrect NVM programming is the most common reason prototypes fail to produce output clocks.
For sub-100 fs RMS jitter performance, isolate the SI5340A-B05364-GM from noisy digital rails by routing VDD through a dedicated ferrite-bead filter network. Reference spurs from switching supplies couple into the MultiSynth divider and degrade jitter to 150-200 fs RMS. Use Skyworks' recommended 4-layer PCB stackup with dedicated ground and power planes for best EMI immunity.
Información de cumplimiento
RoHS and REACH compliance confirmed per Skyworks product page. The Si5340A family is not AEC-Q100 qualified; for automotive applications consult Skyworks' automotive-grade timing portfolio. Halogen-free status not explicitly listed in available data.
