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DS90CR216MTDX/NOPB - 3.3V LVDS 21-Bit Channel Link Receiver | TI
The DS90CR216MTDX/NOPB is a 3.3V LVDS (Low-Voltage Differential Signaling) receiver from Texas Instruments that converts three LVDS data streams and one LVDS clock back into 21 bits of parallel LVCMOS data. It is part of the Channel Link chipset, designed for high-speed data transmission over reduced conductor counts. The device operates from a 3.0V to 3.6V supply and supports LVDS clock rates from 20 MHz to 66 MHz, corresponding to data rates up to 1386 Mbps. It is housed in a 48-pin TSSOP package (also referred to as 48-TFSOP) with a 6.10mm width, and is available in tape and reel packaging. What is an LVDS receiver? LVDS (Low-Voltage Differential Signaling) is a high-speed, low-power interface standard used to transmit data over twisted-pair or PCB traces. An LVDS receiver is a specialized interface IC that converts differential LVDS signals back into single-ended CMOS/TTL logic levels. In the hierarchy of interface ICs, an LVDS receiver falls under the category of high-speed serializers/deserializers (SerDes) and is a key component in display interfaces, industrial video links, and automotive infotainment systems. The DS90CR216 is specifically a deserializer that reconstructs parallel data from a serialized LVDS stream. Key features of the DS90CR216MTDX/NOPB include a 21-bit parallel output, rising-edge data strobe, and backward compatibility with existing 5V Channel Link transceivers (DS90CR213/DS90CR214). The device provides substantial cable reduction: a 21-bit wide data bus plus clock typically requires up to 44 conductors in a single-ended parallel interface, but with Channel Link, only 9 conductors (3 data pairs, 1 clock pair, and ground) are needed. This reduces cable size, cost, and EMI. The receiver also features a power-down mode and supports interconnects up to 5 meters depending on cable quality. Technically, the DS90CR216 uses a differential signaling scheme with a typical differential output voltage of 0.45V, ensuring low electromagnetic interference and high noise immunity. The device is designed for point-to-point or multi-drop configurations and includes internal termination for the LVDS inputs. The rising-edge data strobe simplifies timing by aligning data capture with the clock edge, reducing setup/hold requirements. The receiver is specified for the industrial temperature range of -40°C to +85°C, making it suitable for harsh environments. Typical applications include flat panel display interfaces, digital video transmission, industrial machine vision, and automotive camera links. The DS90CR216 is often paired with the DS90CR215 transmitter to form a complete Channel Link solution. When designing with this device, ensure proper PCB layout with controlled impedance traces for the LVDS pairs and place the receiver close to the connector to minimize skew. Also, provide adequate decoupling on the VCC pins with 0.1uF and 10uF capacitors. In summary, the DS90CR216MTDX/NOPB is a robust, high-speed LVDS receiver that simplifies data transmission in space-constrained applications. Its low-voltage operation and reduced conductor count make it an efficient choice for modern digital interfaces.
DS90CR283MTDX/NOPB - 5V LVDS 28-Bit Channel Link Transmitter | TI
The Texas Instruments DS90CR283MTDX/NOPB is a 28-bit Channel Link transmitter that converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams, with a phase-locked transmit clock transmitted in parallel. Operating from a 4.75V to 5.25V supply, this device supports data rates up to 66 MHz, delivering a total throughput of 1.848 Gbps. Housed in a 56-pin TSSOP (TFSOP) package, it is designed for high-speed point-to-point data transmission over PCB traces or cables, minimizing EMI and reducing interconnect count. Channel Link is a proprietary interface technology developed by National Semiconductor (now part of Texas Instruments) that serializes parallel data into LVDS pairs. This device belongs to the family of LVDS interface ICs, which are used to transmit high-speed digital data with low power consumption and excellent noise immunity. The DS90CR283MTDX/NOPB is the 5V version of the popular DS90CR285, which operates at 3.3V, making it suitable for legacy 5V logic systems. Key features include a 28:4 data compression ratio, a rising-edge data strobe, and a phase-locked loop (PLL) for clock generation. The transmitter accepts 28 single-ended CMOS/TTL inputs and outputs four LVDS data pairs plus one LVDS clock pair. The device supports a wide input clock range and includes a power-down mode to reduce quiescent current. The TSSOP-56 package offers a compact footprint for space-constrained designs. Technically, the DS90CR283MTDX/NOPB uses a differential signaling scheme with a typical output voltage swing of 350 mV across a 100-ohm termination resistor. The LVDS outputs are current-mode drivers that provide low electromagnetic interference (EMI) and high noise immunity. The PLL ensures that the transmitted clock is aligned with the data, simplifying receiver timing. The device is specified for the commercial temperature range (0°C to 70°C) and is RoHS compliant. Typical applications include flat panel displays, digital video interfaces, and high-speed data links in industrial and consumer electronics. The 5V supply makes it ideal for interfacing with legacy TTL logic. When designing with this device, ensure proper termination of the LVDS lines with 100-ohm resistors and maintain controlled impedance on the PCB to preserve signal integrity.
DS90CR482VS - 5.38Gbps 48-Bit LVDS Deserializer | TI
Texas Instruments DS90CR482VS is a 48-bit LVDS Channel Link deserializer operating at 65–112 MHz, with eight differential inputs and 48 parallel CMOS/TTL outputs. The device handles an aggregate data rate of 5.38 Gbps and is packaged in a 100-pin TQFP measuring 14 mm by 14 mm. It is the receiving counterpart to the DS90CR481 serializer and supports high-speed point-to-point data transfer over balanced LVDS links. A deserializer is an interface IC that reconstructs a group of parallel digital signals from serialized differential transmissions. In the LVDS Channel Link hierarchy, the DS90CR482VS belongs to the serializer and deserializer class, within interface ICs and semiconductor signal-conditioning products. Balanced differential signaling improves noise immunity by detecting voltage differences rather than relying on a single conductor referenced to ground. The headline specifications verified for this device are a 48-bit parallel output bus, eight LVDS input channels, a 5.38 Gbps aggregate data rate, and a 65–112 MHz operating frequency range. Its 100-pin TQFP package provides dedicated connections for data, clocking, control, power, and ground. These characteristics make the device relevant to industrial data acquisition, video transport, embedded control backplanes, and other systems that move wide parallel data across a compact cable. The DS90CR482 receives eight differential data inputs and returns 48 parallel outputs. The DS90CR481 description in the supplied material states that the companion transmitter samples 48 CMOS/TTL input bits every transmit-clock cycle and serializes them into eight LVDS streams, with a ninth LVDS link carrying the phase-locked transmit clock. The receiving device reverses this arrangement and reconstructs the parallel data bus. Typical system-level uses include high-speed control links, industrial automation equipment, test systems, video interfaces, and communication equipment. In each case, the principal benefits are reduced connector pin count, lower signal-pickup susceptibility than single-ended transmission, and the ability to move a 48-bit parallel bus across a differential link. Cable length, skew, termination, clocking, and ground-return design remain system-level constraints. Designers should treat the 5.38 Gbps figure as an aggregate signaling rate rather than 5.38 Gbps on every input. Controlled-impedance routing, correct LVDS termination, compliant connector geometry, and verification of inter-pair skew are essential. Exact supply-voltage tolerances, output timing, output capacitance, and recommended passive-component values must be confirmed in the official Texas Instruments datasheet before schematic release. This page consolidates verified distributor inventory and pricing, official product-page information, a verified TI ordering designation, and practical selection guidance. It also clearly identifies electrical and mechanical details that were not present in the supplied source data, preventing unsupported assumptions about voltage ratings, timing, compliance, or pin assignments.
DS90CR563MTD - 65MHz LVDS 18-Bit FPD-Link Transceiver
The National Semiconductor DS90CR563MTD is a 65 MHz LVDS 18-bit color Flat Panel Display FPD-Link transceiver designed for high-speed digital display interfaces. The device is supplied in a 48-pin TSSOP package and combines 21 transmitter outputs with 3 receiver inputs, as identified by the verified distributor classification “21/3 Transceiver FPD-Link, LVDS 48-TSSOP.” Its 18-bit parallel data path is intended for transferring display data between a graphics source and a flat-panel display controller. An FPD-Link transceiver is an interface IC that converts parallel pixel data to a low-voltage differential signaling data stream and receives differential data back from a display panel. It belongs to the FPD-Link interface family, within the broader category of interface ICs and digital semiconductors. LVDS reduces signal amplitude while preserving high data throughput, making it suitable for point-to-point connections between a display timing controller and a panel receiver over cables or board-level interconnects. The verified source data identifies the principal operating features as LVDS signaling, 18-bit color data support, a 65 MHz link clock, 21 driver outputs, 3 receiver inputs, and a 48-pin TSSOP package. These parameters distinguish the device as a multi-channel display-interface solution rather than a general-purpose logic IC. Its transmitter and receiver count also indicates that it is intended for full digital video links carrying pixel data and control information. Technically, the DS90CR563MTD integrates parallel-to-differential and differential-to-parallel conversion into one package. The 65 MHz operating point supports the stated 18-bit color FPD-Link function, while the 21:3 transmit-to-receive arrangement supports simultaneous transfer in both directions. Exact voltage ratings, current consumption, propagation delay, differential impedance, temperature range, and connector or panel-termination recommendations were not present in the verified excerpts and therefore require confirmation from the manufacturer datasheet. Typical uses include LVDS flat-panel monitor links, digital signage interfaces, industrial display controllers, automotive passenger-information displays, and embedded human-machine-interface panels. For these systems, the key selection criteria are the 48-TSSOP footprint, 18-bit color width, 65 MHz clocking, and compatibility with the panel’s LVDS input architecture. System designers must also verify connector assignment and panel timing requirements. The primary layout consideration is the dense 48-pin TSSOP footprint. Place the device according to the datasheet pin configuration and provide the differential routing, ground reference, decoupling, and display-link topology recommended for the application. Do not assume compatibility with a different panel simply because both products use LVDS; data mapping, clocking, voltage levels, and connector assignments must be checked. This product record combines verified device classification, package information, link width, clock rate, distributor listings, and practical replacement guidance. It also identifies where missing electrical and mechanical details must be obtained, preventing unsupported assumptions during schematic review, PCB layout, and production procurement.
DS90LV001TM - 800 Mbps 3.3V LVDS Buffer | Texas Instruments
The Texas Instruments DS90LV001TM is a 3.3 V single-channel LVDS-to-LVDS buffer designed for data rates up to 800 Mbps and supplied in an 8-pin SOIC package. It accepts an LVDS input signal and provides an LVDS output signal for rebuilding and distributing high-speed differential data across backplanes, cable assemblies, and board-to-board links. An LVDS buffer is a low-voltage differential-signaling interface device that improves signal integrity by receiving a differential data stream and retransmitting it as a new LVDS signal. In the technology hierarchy, LVDS signaling belongs to high-speed differential interface electronics, while the DS90LV001TM is specifically a signal buffer rather than a general-purpose logic gate, transceiver, or isolation device. Its buffering function can isolate a transmitter from downstream loading and can help extend usable routing options when transmission-line impedances are controlled. According to the Texas Instruments product page and manufacturer datasheet, key verified features include an 800 Mbps maximum data rate, 3.3 V supply operation, one buffered channel, CMOS technology, and an operating temperature range of -40 °C to +85 °C. The manufacturer describes the part as an LVDS-LVDS buffer, confirming that both the input and output use LVDS signaling. The distributor listings classify the DS90LV001TM as an 8-SOIC signal buffer or re-driver. At the circuit level, the device provides a defined input stage, an internal signal path, and an LVDS output stage intended for controlled-impedance routing. LVDS systems commonly require correct termination, controlled differential impedance, and careful branch or stub management. Because the verified data identifies the part as an 800 Mbps LVDS buffer but does not provide detailed rise-time, jitter, propagation-delay, input-capacitance, output-voltage, or differential-threshold figures, those characteristics should be confirmed in the manufacturer datasheet before release to production. Typical uses include LVDS clock distribution, point-to-point backplane links, cable extension, test and measurement equipment, industrial control systems, and communication equipment. In each case, the buffer is most useful when the source cannot reliably drive the complete downstream load or when regenerated edge behavior is preferable to continuing a lossy transmission-line segment. The principal design task is preserving the intended LVDS signal integrity at 800 Mbps. Use a controlled-impedance PCB layer, place the device close to the relevant connector or receiver, apply the termination scheme specified by the system architecture, and avoid unnecessary stubs. Power and ground pins should have low-impedance bypass connections close to the device. This page combines the verified Texas Instruments product information, distributor inventory references, package details, compatible orderable variants, and practical LVDS design guidance. It also distinguishes electrically equivalent catalog variants from true functional alternatives and identifies where detailed electrical, pricing, or lifecycle data still requires manufacturer confirmation.
DS90LV001TMX/NOPB - 800 Mbps LVDS Buffer | Texas Instruments
The Texas Instruments DS90LV001TMX/NOPB is a single-channel LVDS-to-LVDS buffer / re-driver that supports signaling rates up to 800 Mbps in an 8-pin SOIC (D) package with an exposed thermal pad area. The device takes a standard LVDS input signal and re-transmits an LVDS signal at the output, while operating from a single 3.3 V supply (3.0 V to 3.6 V) and consuming roughly 70 mA of supply current. It is qualified across the -40 C to +85 C industrial temperature range and is supplied in a tape-and-reel SOIC-8 package on a 3.90 mm body width. An LVDS buffer (Low-Voltage Differential Signaling buffer / re-driver) is a type of high-speed differential interface IC that regenerates and re-shapes a weak or distorted differential signal so it can drive another transmission line segment. In the broader system hierarchy it sits under interface ICs, then signal-conditioning devices, and ultimately under wired-connectivity semiconductors. LVDS buffers are essential building blocks in any system where the original LVDS transmitter cannot source enough current to reach a distant receiver while still meeting the TIA/EIA-644 eye-diagram mask. Key features of the DS90LV001TMX/NOPB include a 2.0 ns typical propagation delay, low jitter and low skew design that holds the differential output within tight limits, integrated 100 ohm input termination across the LVDS input pair, and an LVDS output stage that supports both point-to-point and multi-drop topologies. The device is designed to accept LVPECL inputs when AC-coupled, giving it cross-standard compatibility within the same SOIC-8 footprint. A single channel is provided per package, and the part is pin-to-pin compatible with the rest of the DS90LV001 family. Architecturally, the DS90LV001 uses a current-mode LVDS driver with on-chip bias generation. The differential receiver detects the incoming signal and re-times it through an internal logic stage that drives the output current-steering network. Because the part is a transparent buffer, it does not add protocol encoding or clock-data recovery - it simply regenerates the differential edge, restoring amplitude and common-mode level so the signal can traverse another cable, connector, or FR-4 stub. Typical applications for the DS90LV001TMX/NOPB include clock distribution across backplanes, buffering LVDS links between mezzanine cards, extending FR-4 trace runs in telecom and networking line cards, cable driving in point-to-point LVDS links, and acting as a stub-length isolator in large distributed systems where the unterminated stub length would otherwise limit the maximum achievable data rate. Designers also use it as a fan-out repeater when one LVDS source must drive two downstream loads. A key design consideration is the placement of external AC-coupling capacitors when LVPECL sources must be interfaced - these capacitors must be placed close to the device inputs to control the common-mode voltage. The DS90LV001's 8-pin SOIC footprint keeps the layout small but thermal performance is modest, so for applications that require higher output drive or multi-channel operation a higher-current or multi-channel LVDS part from the same family should be considered. This page synthesizes distributor stock, drop-in SOIC-8 alternatives, and practical PCB-layout notes not found in the manufacturer datasheet.
DS90LV017MX - 155Mbps LVDS Driver | Texas Instruments
The Texas Instruments DS90LV017MX is a single-channel LVDS differential driver with a 155 Mbps data rate, 3 V to 3.6 V supply range, and an 8-SOIC package. It converts one CMOS input into a balanced LVDS differential output for high-speed point-to-point communication links. The device is specified for 0°C to 70°C operation and is packaged in an 8-pin SOIC, making it suitable for industrial and commercial equipment requiring a compact differential line driver. An LVDS differential driver is an interface IC that transmits data across a balanced copper connection. LVDS, or Low-Voltage Differential Signaling, belongs to the interface IC family and uses complementary differential signals to improve noise immunity and reduce electromagnetic interference compared with single-ended logic. The DS90LV017MX provides one driver channel in a small 8-SOIC package for systems that need a single high-speed differential output. Key features include one LVDS driver channel, a 155 Mbps maximum data rate, operation from 3 V to 3.6 V, and a 0°C to 70°C operating-temperature range. The reported operating voltage allows the driver to be used with 3.3 V system rails, while the LVDS output supports low-voltage, high-speed signaling across suitable board-level or balanced-cable interconnects. The package is specified as 8-SOIC, with a 0.154 inch, 3.90 mm body width. The DS90LV017MX is intended for point-to-point links where a transmitter must launch a compliant differential signal into a controlled impedance interconnect. Because LVDS relies on balanced signaling, the receiving device, trace geometry, connector, and terminations determine whether the intended signal integrity and data-rate margins are achieved. The driver is therefore best suited to applications where the complete channel has been characterized rather than relying on the IC alone. Typical applications include industrial control links, test and measurement equipment, computer peripherals, point-to-point backplanes, and embedded communication interfaces. Its single-driver configuration makes it useful when a system needs one LVDS transmit path and requires a small package. The 0°C to 70°C temperature range supports commercial and industrial environments within that specified range. When designing around the DS90LV017MX, verify the input amplitude, supply sequencing, output termination, differential trace impedance, and receiver compatibility in the complete channel. The 3 V to 3.6 V supply range requires a valid 3.3 V rail, and the 0°C to 70°C rating must be checked against the equipment enclosure temperature. This product page consolidates distributor availability, package information, operating limits, verified cross-reference results, and practical selection guidance into one engineering-oriented reference for the DS90LV017MX LVDS driver.
DS90LV019TM - 3.3V/5V LVDS Transceiver | Texas Instruments
The Texas Instruments DS90LV019TM is a 3.3 V or 5 V low-voltage differential signaling transceiver containing one differential driver and one differential receiver in a 14-pin SOIC package. It supports data rates up to 100 Mbps and accepts TTL/CMOS-compatible driver inputs while providing a CMOS-compatible receiver output. The device is intended for high-speed, low-power point-to-point interconnects where differential signaling improves noise immunity and reduces EMI. An LVDS transceiver is an interface IC that converts a single-ended logic signal into a low-voltage differential pair on the transmit side and converts a received differential pair back into a single-ended logic signal on the receive side. In the signal-chain hierarchy, DS90LV019TM is an LVDS interface transceiver, belonging to the broader interface-IC and data-communications semiconductor categories. Its differential signaling is associated with the EIA-644-A and TIA-644-A technologies identified in the verified component data. Key features include independent operation of the driver and receiver, support for both 3.3 V and 5 V supplies, and a 3.5 mA LVDS output loop current. The 14-pin SOIC package uses a flow-through pin arrangement that permits short PCB routing between device pins and an external connector. A maximum data rate of 100 Mbps makes the device suitable for moderate-speed point-to-point links rather than very high-speed multimode channels. The architecture uses a current-mode differential driver to maintain controlled output current while transferring data across a balanced connection. Because the two transmission lines carry complementary signals, external circuitry reconstructs the logic state from their voltage difference. This approach can reduce sensitivity to common-mode noise relative to an unbalanced single-ended link, provided the receiver termination, connector, and cable geometry satisfy the interface requirements. Typical uses include industrial control links, test and measurement equipment, computer peripherals, video or display interconnects, and embedded systems that need a compact LVDS point-to-point interface. Because the driver and receiver are independent, a board can transmit and receive over separate balanced pairs. The 14-pin SOIC package is also suitable for conventional surface-mount PCB assembly where sufficient copper and solder mask clearance are available. Designers should preserve the flow-through routing advantage and keep LVDS traces short, properly terminated, and referenced to a continuous ground plane. Input and output logic levels must remain compatible with the selected 3.3 V or 5 V supply. Because the supplied excerpts do not provide a verified pin-number-to-pin-name table, the pinout is intentionally left unpopulated rather than presenting inferred connections as authoritative data. This page combines verified manufacturer and distributor information, package details, interface characteristics, application guidance, and strict drop-in equivalence analysis. It also distinguishes electrically similar parts that use a different package and therefore cannot be treated as true PCB drop-in replacements.
DS90LV027MX - Dual 600Mbps LVDS Driver | Texas Instruments
Texas Instruments DS90LV027MX is a dual CMOS LVDS differential driver optimized for high-data-rate, low-power signal transmission. It supports data rates in excess of 600 Mbps, operates from a nominal 3.3 V supply, and is packaged in an 8-lead SOIC. Each channel uses a current-mode differential driver, while the device’s flow-through pin arrangement simplifies high-speed PCB routing. According to the Texas Instruments product page, the driver maintains low power dissipation at high frequency and minimizes short-circuit fault current. Its differential outputs typically swing about 340 mV, providing low EMI while transferring clock and data signals. The DS90LV027MX is therefore positioned between general-purpose logic interfaces and the broader LVDS interface-IC category, where differential signaling, controlled output current, and low-noise operation are central requirements. An LVDS driver is a line and bus driver that converts a low-voltage CMOS logic input into a balanced differential output. Because LVDS transmits information as the voltage difference between two conductors, it can support high data rates while reducing sensitivity to common-mode noise and limiting electromagnetic emissions. The DS90LV027MX includes two independent differential drivers, allowing clock, data, control, or serial-interface signals to be transmitted in parallel. Its dual-channel architecture increases routing flexibility while conserving board area compared with two separate single-channel devices. The manufacturer describes the DS90LV027 as a current-mode driver optimized for high-data-rate and low-power operation. This architecture helps power dissipation remain low as operating frequency increases and also reduces the short-circuit fault current available from the outputs. Differential output swing is typically 340 mV, which supports LVDS-compatible receivers and limits output voltage excursions. The 8-lead SOIC package uses a flow-through layout intended to make PCB layout easier, particularly when traces must pass through or around the device on high-speed digital boards. The verified device information identifies DS90LV027MX as a 2/0 LVDS driver in an 8-SOIC package. The related lead-free DS90LV027MX/NOPB listing identifies a 3.0 V to 3.6 V supply range, while Mouser lists the commercial-temperature variant at 0°C to 70°C. The DS90LV027 family is designed for data rates in excess of 600 Mbps, equivalent to more than 300 MHz of serialized information according to the family description. The current-mode implementation and controlled differential swing help balance high throughput, power consumption, and EMI control. Typical uses include clock distribution, parallel-to-serial data links, industrial-control interfaces, test and measurement equipment, video timing links, and communications systems that transmit high-speed clock or data over balanced lines. Because the DS90LV027MX provides two differential outputs, a board designer can use one channel for a clock and another for data, or deploy two independent data streams. In each case, the receiver, cable, connector, and PCB geometry must be designed consistently with LVDS signal integrity requirements. The most important layout consideration is to preserve controlled differential impedance and minimize the distance over which the two traces of a pair are separated. Place decoupling close to the supply pins, route the differential pair as a tightly coupled pair, and avoid unnecessary stubs or test-point discontinuities. The 8-lead SOIC footprint is easy to source, but package parasitics, connector transitions, and imperfect pair geometry can still reduce the practical benefit of the device’s high supported data rate. This product page combines the verified Texas Instruments and distributor information with package, application, selection, and design guidance. It also distinguishes confirmed ordering variants from unsupported substitutes and identifies every parameter that still requires confirmation from the manufacturer datasheet or distributor record.
DS90LV028ATM - Dual 400 Mbps LVDS Receiver | Texas Instruments
Texas Instruments DS90LV028ATM is a dual CMOS differential line receiver for Low Voltage Differential Signaling (LVDS) data links, supporting data rates in excess of 400 Mbps (200 MHz) in an 8-pin SOIC package. The receiver accepts a typical differential input voltage of 350 mV and converts each LVDS input into a CMOS-compatible logic output. Its dual-channel architecture allows one package to receive two independent low-voltage differential signals. An LVDS receiver is an interface IC within the broader line-receiver and interface-IC hierarchy. LVDS is a differential signaling technology in which data is transmitted as the voltage difference between two complementary conductors. That architecture provides useful noise immunity for high-speed links, while the receiver converts the small differential signal into a single-ended CMOS output that can be processed by digital logic, a controller, or a field-programmable gate array. According to the Texas Instruments DS90LV028A product page, the device is designed for applications requiring ultra-low power dissipation, low noise, and high data rates. The verified technical summary identifies a maximum data rate in excess of 400 Mbps, equivalent to a 200 MHz parallel data rate. The related distributor data also identifies a 3 V supply class, a 1.5 ns receiver performance figure, and approximately 9 mA of operating current, although the exact test conditions are not included in the supplied excerpts. The DS90LV028A family provides two independent receiver channels, making it useful in point-to-point industrial links, test and measurement equipment, instrumentation, and backplane communication. The 8-pin SOIC footprint simplifies assembly in designs that already use conventional surface-mount packages. Because LVDS is a differential interface, each receiver channel requires a matched differential input and appropriate cable or board-level termination. Designers should preserve the receiver's common-mode operating limits, provide the specified termination network, and maintain a controlled return path between the transmitter and receiver. Differential routing on the printed circuit board should minimize impedance discontinuities and keep the pair length-matched. The receiver should also be evaluated for fail-safe behavior when the cable is open, shorted, or terminated because those conditions affect receiver metastability and output state. This product page consolidates the verified manufacturer specifications, distributor identifiers, package information, application guidance, and substitution constraints for DS90LV028ATM. It also distinguishes a true pin-compatible replacement from similar LVDS receivers that require a different pinout, circuit modification, or data-rate tradeoff.
DS90LV047ATMTC/NOPB - 400 Mbps LVDS Quad Driver | TI 16-TSSOP
The Texas Instruments DS90LV047ATMTC/NOPB is a 400 Mbps (200 MHz) quad CMOS flow-through differential line driver implementing Low Voltage Differential Signaling (LVDS) technology, housed in a 16-pin TSSOP package. The device accepts LVTTL/CMOS input levels and translates them to a 350 mV differential LVDS output, providing ultra-low power dissipation and high data rates for point-to-point high-speed interface applications. A line driver in the LVDS family is a transceiver front-end component that converts single-ended logic levels into a low-voltage differential pair, and the DS90LV047A belongs to that LVDS sub-family which also includes line receivers (DS90LV048A), transceivers (DS90LV049), and serializers/deserializers. Within the broader hierarchy of interface ICs, LVDS drivers sit under differential signaling ICs, which themselves sit under interface ICs, then under wired-connectivity ICs, and finally under integrated circuits. The DS90LV047A and companion line receiver DS90LV048A provide an alternative to high-power pseudo-ECL devices, offering CMOS-level power consumption with multi-hundred-megahertz switching speeds. Key features include four independent drivers with flow-through pinout, typical differential output swing of 350 mV across a 100 ohm load, support for data rates in excess of 400 Mbps (200 MHz toggle rate), and 3.3 V nominal supply operation from 3.0 V to 3.6 V. Flow-through pin ordering simplifies PCB routing by allowing the input on one side and the LVDS output on the opposite side, which reduces layer count and via usage. The architecture uses a current-mode LVDS driver stage with on-chip termination, providing controlled edge rates, low EMI, and robust common-mode noise immunity. The wide common-mode range on the differential pair and the LVDS standard's inherent noise margin allow reliable transmission over FR-4 backplanes and ribbon cable at lengths exceeding several meters. Typical applications include LCD display row/column drivers, board-to-board high-speed data links, clock distribution networks, printers and copiers, network switches and routers, and backplane interconnect for telecommunications equipment. The device is also commonly paired with the DS90LV048A quad receiver to form complete LVDS links. When designing with this device, maintain a 100 ohm differential termination at the receiver end of the pair, place decoupling capacitors close to the VCC pin, and keep differential traces matched within 10 mil to preserve duty-cycle balance and minimize reflections. This page synthesizes distributor pricing, drop-in TSSOP alternatives, and practical design guidance not found in the manufacturer datasheet.
DS90LV047ATMTCX - 400Mbps Quad LVDS Driver | Texas Instruments
The Texas Instruments DS90LV047ATMTCX is a 400 Mbps quad CMOS flow-through differential line driver with four LVDS transmitters, a 3 V to 3.6 V supply range, and a 16-pin TSSOP (PW) package. It converts low-voltage TTL/CMOS inputs into low-voltage differential LVDS outputs for high-speed point-to-point interfaces. The device supports data rates in excess of 400 Mbps, equivalent to more than 200 MHz according to the manufacturer product page. An LVDS differential line driver is an interface IC that transmits complementary signals through a balanced pair. Because the two conductors carry equal and opposite signals, the transmitted signal is less susceptible to common-mode noise than a single-ended interface. This makes the DS90LV047A family suitable for links requiring low power consumption, high data rates, and reliable point-to-point signal transfer across a board or cable. The principal verified features are four differential outputs, a 3 V to 3.6 V supply, a 400 Mbps signaling rate, and low-voltage differential signaling. The flow-through architecture supports signal routing where data enters and exits on corresponding package sides. The manufacturer identifies the device as an alternative to high-power pseudo-ECL devices in high-speed point-to-point interface applications. The DS90LV047ATMTCX is a line driver rather than a receiver, ADC, DAC, or transceiver. Each of its four channels accepts TTL or CMOS logic and produces an LVDS differential output. The 16-pin TSSOP package is suitable for compact surface-mount layouts, while the quad-channel arrangement reduces the number of interface ICs needed when several independent links are required. Typical applications include high-speed backplanes, point-to-point industrial links, digital video and control paths, communications equipment, and instrumentation requiring reliable differential transmission. The companion DS90LV048A family provides line receivers, allowing a transmitter and receiver pair to be designed into a complete LVDS link. For PCB design, place the driver close to the source device, route differential pairs with matched geometry, and keep the pair away from unrelated high-current switching nodes. Confirm LVDS output amplitude, receiver compatibility, termination, and edge-rate requirements using the manufacturer datasheet before releasing a new layout. This page combines verified manufacturer and distributor information with practical interface design guidance, application context, and replacement considerations that are not present in a raw distributor listing.
DS90LV048ATMTCX - 400 Mbps Quad LVDS Receiver | TI
Texas Instruments DS90LV048ATMTCX is a four-channel CMOS flow-through differential line receiver that supports LVDS data rates above 400 Mbps (200 MHz), operates from a 3 V to 3.6 V supply, and is packaged in a 16-pin TSSOP (PW). It converts four low-voltage differential inputs into four CMOS outputs. An LVDS receiver is an interface circuit that recovers a digital signal from a low-voltage differential pair. LVDS belongs to differential line-driver and receiver technology within interface ICs. Its two-wire differential signaling helps reject common-mode noise, while the receiver converts the small differential voltage into a logic-level signal for downstream digital equipment. Key verified features include four differential receivers, data rates in excess of 400 Mbps, a typical differential input signal of 350 mV, and a 3 V to 3.6 V supply range. The flow-through architecture supports high-speed point-to-point links while its CMOS outputs connect the recovered data to controllers, FPGAs, test equipment, or other digital logic. The DS90LV048A family is positioned for low-power, high-rate LVDS communication. Unlike a single-channel receiver, this quad device consolidates four channels into one package. Its supply voltage matches the provided DS90LV048A product description, while the 16-TSSOP package supports conventional surface-mount assembly. Exact propagation delay, input thresholds, output timing, and current limits are not supplied in the verified excerpts and therefore are not inferred here. Typical uses include multi-channel digital backplanes, point-to-point data links, industrial control interfaces, communications equipment, and FPGA or controller connectivity. The receiver is most appropriate where four LVDS pairs must be converted to CMOS logic on a 3.3 V system. Designers should preserve the differential pair geometry, provide a clean reference ground, route the two members of each pair together, and verify input common-mode and timing requirements against the complete manufacturer datasheet. The verified source identifies DS90LV048A rather than a complete revision-specific pin table for this exact orderable suffix. This page combines manufacturer and distributor findings with package, application, lifecycle, and purchasing guidance while clearly separating verified facts from unavailable electrical details.
DS90UB947TRGCRQ1 - 1080p oLDI Dual FPD-Link III Serializer | TI
The Texas Instruments DS90UB947TRGCRQ1 is a 1080p OpenLDI (oLDI) to FPD-Link III dual serializer with up to 3.36 Gbps forward-link data rate, packaged in a 64-pin VQFN (RGC) 9x9 mm with exposed thermal pad. It converts parallel RGB/YCbCr video plus I2S audio and control data into a single differential pair for transmission over STP/AWG cable to a matching DS90UB948/DS90UH948 deserializer. What is a serializer/deserializer (SerDes) channel? A serializer is a mixed-signal interface IC that compresses a wide parallel bus (LVCMOS color, sync, audio, control) into a high-speed serial differential link using embedded clock technology. FPD-Link III is TI's proprietary SerDes family used for automotive and industrial displays where EMI, cable weight, and connector count must be minimized. A serializer sits on the SoC/FPGA side of the harness and a deserializer on the display side, replacing 20-30 LVDS lanes with a single twisted pair. Key features of the DS90UB947TRGCRQ1 include 3.36 Gbps forward channel, a 40 kbps to 1 Mbps back-channel return path for touch/control data, support for WUXGA (1920x1200) and 1080p60 in non-reduced-blanking mode, multi-channel I2S audio, and adaptive equalization at the deserializer side. The device supports up to 24-bit color depth and offers backward-compatible operation at WXGA and 720p over a single link. The device uses low-voltage differential signaling (LVDS), data scrambling, and randomization to minimize EMI - critical for CISPR 25 Class 5 automotive compliance. Internal pattern generation and BIST modes allow in-system link validation without external equipment. Typical applications include automotive infotainment head units, ADAS driver-assist displays, rear-seat entertainment, instrument clusters, and industrial HMI panels where a single twisted pair must replace wide parallel RGB harnesses. When designing with the DS90UB947TRGCRQ1, choose a matched DS90UB948-Q1 (1080p) or DS90UH948-Q1 (4K) deserializer, plan for 100-ohm differential routing of the FPD-Link III pair, and use TI's WEBENCH FPD-Link III tool to validate cable length and pre-emphasis settings. This page synthesizes distributor pricing, AEC-Q100 qualification evidence, drop-in package-compatible alternatives, and practical PCB layout notes not found in the manufacturer datasheet alone.
DS90UB948TNKDRQ1 - 1080p FPD-Link III Deserializer | Texas Instruments
The Texas Instruments DS90UB948TNKDRQ1 is a 1080p oLDI Dual FPD-Link III Deserializer that converts 1-lane or 2-lane FPD-Link III serial streams back into an OpenLDI (FPD-Link) parallel interface, supporting up to 3.36 Gbps throughput per lane and housed in a 64-pin WQFN (9x9 mm) package. Designed to pair with the DS90UB949A-Q1, DS90UB949-Q1, or DS90UB947-Q1 serializers, it recovers clock, video data, control, and GPIOs over cost-effective 50 ohm single-ended coaxial or 100 ohm differential shielded twisted-pair (STP) cabling. The device supports dual LVDS output ports (Port 0 and Port 1) with a maximum output data rate of 3.36 Gbps and is AEC-Q100 qualified for automotive camera, infotainment, and instrument-cluster applications. Operating from a 1.8 V supply, the deserializer integrates adaptive equalization, clock data recovery, and dual-link OpenLDI formatting for resolutions up to 1920x1080p at 60 Hz. An FPD-Link III deserializer is a serializer-deserializer (SerDes) receiver IC that converts high-speed serialized LVDS-style differential streams into a parallel RGB/LVDS display interface, enabling long-reach video transmission over a minimal wire count while embedding a bidirectional control channel and DC-balanced data scrambling for EMI reduction. In the broader system taxonomy, this device sits inside interface ICs -> serializer/deserializer (SerDes) -> automotive video interface, sitting above physical-layer transceivers and below the display timing controller. Key features include dual-port LVDS/OOpenLDI output, integrated adaptive receiver equalization supporting up to 10 m of coax or 15 m of STP cable at full speed, I2C-compatible control channel with up to 400 kHz pass-through, 9+ bidirectional GPIOs, hardware BIST (Built-In Self-Test), and an INT/AT power protection profile. The 64-pin WQFN package with exposed thermal pad provides low thermal resistance for automotive-grade operating temperature ranges. The device is suitable for ADAS surround-view, rear-view, and e-mirror camera systems that demand high-bandwidth uncompressed video over robust automotive cabling. Typical applications include automotive 1080p camera deserialization for ADAS platforms, surround-view and rear-view camera hubs, digital instrument cluster displays, in-vehicle infotainment (IVI) head units, and LVDS-to-OOpenLDI bridge designs replacing legacy parallel RGB links. When designing, place 0.1 uF and 1 uF decoupling capacitors adjacent to each supply pin and route the FPD-Link III differential traces as a 100 ohm differential pair with controlled 50 ohm single-ended impedance for coax variants.
DS90UH949TRGCTQ1 - 1080p HDMI to FPD-Link III Bridge | TI
The Texas Instruments DS90UH949TRGCTQ1 is a 1080p HDMI-to-FPD-Link III bridge serializer with HDCP support, supplied in a 64-pin VQFN (RGC) package (9 mm x 9 mm) with exposed thermal pad. It serializes HDMI input up to WXGA and 720p resolutions at 24-bit color depth in backward-compatible mode, and up to 1080p with deep color support in FPD-Link III mode, delivering 5.95 Gbps over a single differential pair to a paired FPD-Link III deserializer such as the DS90UH928Q or DS90UH940-Q1. Key specifications include a 5.95 Gbps forward-channel data rate (up to 2.975 Gbps per lane), integrated HDCP 1.4 cipher engine for content-protected video transport, an embedded clock over the bidirectional control channel, and an I2C-compatible pass-through interface for remote peripheral access. The device accepts up to three digital-input video sources and provides an adaptive equalization receiver on the back-channel, enabling operation across long-distance STP or coaxial cables commonly used in automotive infotainment backbones. A serializer/deserializer pair, often abbreviated SerDes, is a fundamental building block of modern in-vehicle video distribution. SerDes converters sit in the signal chain between a graphics source (HDMI, DSI, OpenLDI) and a remote display panel, compressing parallel RGB/clock lines into a high-speed serial stream and embedding the clock in the data - which dramatically reduces wiring harness count, EMI, and connector pin count. FPD-Link III is TI's third-generation Flat Panel Display Link family, designed for AEC-Q100-qualified automotive display modules; it adds HDCP content protection, bidirectional I2C/audio transport, and adaptive equalization on top of the original FPD-Link II architecture. A differential output architecture and integrated PLL with low jitter reduce the need for external clock-recovery components. Automotive-grade qualification (AEC-Q100) makes the DS90UH949TRGCTQ1 a drop-in solution for head-unit-to-display video transport in instrument clusters, center-stack displays, and rear-seat entertainment. Compatibility with backward-mode 24-bit color and reduced blanking formats lets the same part serve legacy panels. Typical applications include automotive head-unit video links, digital instrument clusters, HUD projectors, and rear-seat entertainment displays. The DS90UH949TRGCTQ1 also serves industrial touch-panel bridges and medical imaging displays where HDCP-protected video must traverse long cables. The device pairs naturally with the DS90UH940-Q1 deserializer for full HDCP-end-to-end support. When designing with this part, follow TI's reference layout for the 64-VQFN exposed pad, which provides the primary thermal path; insufficient solder coverage will derate the thermal envelope. Use AC-coupled interconnects on the FPD-Link III output, keep the HDMI input traces impedance-controlled at 100 ohms differential, and place the local 1.8 V/3.3 V decoupling within 5 mm of each supply pin. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
E-L9637D013TR - ISO 9141 K-Line Bus Driver/Transceiver | STMicroelectronics
The STMicroelectronics E-L9637D013TR is a monolithic ISO 9141 K-Line bus driver and transceiver designed for automotive on-board diagnostics (OBD-II) and bidirectional serial communication, packaged in an 8-pin SOIC (SO-8, 0.154 inch/3.90 mm width) and shipped in Tape & Reel (TR). It operates from a wide 4.5 V to 36 V supply, tolerates 40 V transients, and survives reverse-battery connection down to VS = -24 V while drawing approximately 2.3 mA supply current. What is a K-Line / ISO 9141 transceiver? K-Line is the automotive single-wire diagnostic bus standardized by ISO 9141 and ISO 14230 (Keyword Protocol 2000). It typically operates at ~10.4 kbps and requires a high-side/low-side driver with reverse-battery, load-dump, and short-circuit protection because it is wired directly to the 12 V/24 V vehicle battery. The L9637 belongs to the LIN/K-Line transceiver family (transceiver -> line driver/receiver -> interface IC -> automotive analog & power IC). Key features include K output current limitation of typ. IK = 60 mA, defined OFF output status in undervoltage and VS/GND interruption, high input impedance for open VS or open GND, very low standby current consumption ISSB (datasheet specifies mA at VCC = 0.5 V), and integrated reverse-battery/overvoltage safeguards. The 1A.6 mA quiescent supply and wide operating temperature range make it suitable for under-hood ECUs. Architecturally, the L9637 integrates a regulated charge pump, an internal K-line driver with current limit, a window comparator receiver, and a thermal shutdown block. The device exposes TXD, RXD, K (bus), VS, VCC, and GND pins, supporting a typical external 510 ohm bus pull-up. Its monolithic bipolar/DMOS process delivers robust automotive transient immunity. Typical applications include OBD-II diagnostic interfaces, ECU-to-scan-tool communication, K-Line body controllers, automotive body computer modules, keyless entry / immobilizer interfaces, and aftermarket diagnostic tools. Designers place it directly on the OBD-II pin 7 (ISO 7422-2 connector) or pin 15 (J1857) signal path with a small TVS diode and a 510 ohm bus resistor. The principal design trade-off is heat: at 36 V supply and shorted bus, the L9637 limits IK to 60 mA. Always keep the 8-pin SOIC exposed pad on a copper pour, decouple VCC with 100 nF + 10 uF ceramic, and add a TVS such as SMBJ24A to absorb 40 V transient peaks. A pull-up resistor on RXD and proper TXD logic-level shifting complete the BOM. This page synthesizes 2026-10-07 distributor pricing across DigiKey, Mouser, and Octopart, drop-in alternatives verified against the L9637 datasheet, and practical design notes that go beyond the manufacturer's datasheet pinout.
ENC28J60-I/ML - 10BASE-T Ethernet Controller | Microchip
The Microchip Technology ENC28J60-I/ML is a 28-pin, 10BASE-T stand-alone Ethernet controller with an integrated MAC and PHY, 8 Kbytes of packet-buffer RAM, and an SPI serial interface in a 28-QFN package measuring 6 mm by 6 mm. It combines Ethernet physical-layer and media-access-control functions in one component, reducing the board area and external circuitry required for an embedded network interface. An Ethernet controller is a semiconductor that manages packet transmission and reception between a host processor and an Ethernet physical layer. The ENC28J60 belongs to the stand-alone Ethernet controller category rather than a conventional high-speed Ethernet MAC IC. Its integrated 10BASE-T PHY connects directly to 10BASE-T network hardware, while the SPI interface allows a microcontroller or other SPI host to access registers and packet buffers. Key features include IEEE 802.3-compatible 10BASE-T operation, an integrated MAC and PHY, 8 Kbytes of transmit and receive packet buffer memory, and a compact 28-QFN package. The SPI interface provides a straightforward connection to embedded processors, while the integrated PHY reduces the number of active components needed for a basic Ethernet endpoint. The 6 mm by 6 mm package also supports space-constrained embedded equipment. The ENC28J60-I/ML is intended for low-speed 10BASE-T networks rather than Fast Ethernet designs. Its architecture is appropriate when low network throughput, low component count, and a simple host interface are more important than 100BASE-TX performance. The ENC28J60 supports 8 Kbytes of buffer RAM for packet handling, while the SPI host controls the device through its command and register set. Typical applications include embedded Ethernet bridges, industrial monitoring equipment, access-control systems, building automation nodes, laboratory instruments, and small network-connected controllers. These systems can use the integrated PHY to avoid a separate Ethernet transceiver while retaining a conventional SPI connection to a microcontroller. A primary design consideration is the distinction between the 10BASE-T ENC28J60 and the 100BASE-TX ENC424J600. The ENC424J600 supports faster Ethernet but uses a different package and requires a different PCB layout. Designs should not treat those devices as footprint-compatible replacements. Confirm magnetics, RJ-45 integration, grounding, decoupling, and signal-integrity requirements in the manufacturer application guidance before releasing the layout.
ENC28J60-I/SO - 10BASE-T SPI Ethernet Controller | Microchip
The Microchip Technology ENC28J60-I/SO is a 28-pin stand-alone 10BASE-T Ethernet controller with an integrated MAC, integrated 10BASE-T PHY, 8 KB packet-buffer SRAM, and an SPI serial interface. It operates from a 3.3 V supply, supports an IEEE 802.3-compatible Ethernet interface, and is packaged in a 28-pin SOIC. The device is intended for embedded systems that need a compact Ethernet endpoint without a separate Ethernet controller and PHY. An Ethernet controller is an interface IC that connects a microcontroller or processor to a physical Ethernet network. The MAC manages Ethernet frames and access to the transmit/receive buffer, while the PHY handles the physical-layer signaling. The ENC28J60 combines these functions with an SPI host interface, making it part of the network-controller and interface-IC hierarchy rather than a general-purpose microcontroller. Verified product information identifies an integrated MAC and PHY, 8 KB of buffer RAM, a 10BASE-T Ethernet interface, and SPI connectivity. The ENC28J60 is designed to operate with a 25 MHz parallel-resonance crystal connected between OSC1 and OSC2, as described in the manufacturer data sheet. A 3.1 V to 3.6 V supply range and -40°C to +85°C operating range are reported by the retrieved distributor data. Typical uses include microcontroller-based monitoring equipment, industrial control modules, data loggers, laboratory instruments, IoT gateways, and embedded network bridges. The SPI host interface allows the host processor to configure the controller and transfer Ethernet frames, while the integrated PHY reduces the number of external network-interface components. Designers should provide the required clock network, bypass capacitors, Ethernet magnetics, RJ45 connectivity, and a power supply that stays within the verified 3.1 V to 3.6 V range. Firmware must implement the network stack required by the application because the verified product description identifies the device as a controller with SPI rather than a device with an integrated TCP/IP stack.
ENC28J60-I/SP - 10BASE-T SPI Ethernet Controller | Microchip
The Microchip Technology ENC28J60-I/SP is a 28-pin, 10BASE-T stand-alone Ethernet controller with an integrated MAC and PHY, 8 Kbytes of buffer RAM, and an SPI serial interface, supplied in a 28-pin SPDIP package. Its 10 Mbps Ethernet capability and three-wire SPI host interface make it suitable for embedded systems that need a compact, low-cost network connection without a dedicated external Ethernet controller. The device operates from a 3.1 V to 3.6 V supply and supports the industrial temperature range of -40°C to +85°C according to the verified product data. What is an Ethernet controller? An Ethernet controller is an interface IC that connects a host processor to a physical Ethernet network. The ENC28J60 family combines a Media Access Control layer, a 10BASE-T physical layer, packet buffer memory, and an SPI interface in one device. In the hierarchy of semiconductor components, it is an Ethernet interface controller, a network interface IC, and a power-management-compatible embedded peripheral for connected embedded products. The principal verified features are the integrated MAC and PHY, 8 Kbytes of buffer RAM, SPI connectivity, 10BASE-T operation at 10 Mbps, a 3.1 V to 3.6 V operating supply range, a maximum supply current of 180 mA, and 28 pins. The integrated PHY reduces the number of external network-interface components required, while the serial interface allows a microcontroller to control packet transfer over SPI. The -40°C to +85°C industrial range makes the -I/SP grade appropriate for industrial and other extended-temperature equipment, subject to application-specific qualification. The ENC28J60-I/SP is a hardware network interface rather than a complete TCP/IP stack. The host processor therefore requires suitable networking software to implement the required protocols. Its 10BASE-T operation is appropriate for legacy or cost-sensitive embedded Ethernet links, but it is not a 100BASE-T replacement. The integrated 8 Kbytes of buffer RAM helps coordinate packet storage between the Ethernet interface and the SPI host, while the small 28-pin package simplifies prototype and through-hole assembly. Typical uses include industrial monitoring equipment, embedded control systems, serial-to-Ethernet gateways, automated test equipment, and connected instrumentation. In these applications, the controller can sit between a microcontroller and an RJ45 or magnetics-based Ethernet network interface, while the host processor handles application data and higher-level networking. The SPI bus provides a practical connection to microcontrollers and other embedded processors. A key design consideration is that the ENC28J60-I/SP is designed around 10BASE-T operation and requires careful implementation of the network interface, clock circuitry, decoupling, and PCB layout. Verify the complete pin assignment, recommended external components, and timing requirements against the manufacturer datasheet before layout release. This page combines verified manufacturer and distributor information, practical application guidance, and explicit comparison data to support component selection.
ENC28J60-I/SS - 10BASE-T Ethernet Controller | Microchip
The Microchip Technology ENC28J60-I/SS is a 28-pin, stand-alone 10BASE-T Ethernet controller with an integrated MAC and PHY, 8 KB of buffer RAM, and an SPI serial interface in a 28-pin SSOP package. It operates from a 3.1 V to 3.6 V supply at an indicated supply current of 180 mA, while supporting an industrial operating temperature range of -40°C to +85°C. The integrated Ethernet functionality allows a host microcontroller to communicate over 10BASE-T without adding a separate MAC or physical-layer transceiver. An Ethernet controller is a network-interface semiconductor that connects an embedded host to a physical Ethernet network. The ENC28J60-I/SS combines three major functions in one device: a Media Access Controller for Ethernet frame handling, a 10BASE-T PHY for physical-layer signaling, and an SPI interface for register access and packet-buffer transfers. Within the broader hierarchy, it is an Ethernet interface controller, an interface IC, a network semiconductor, and ultimately a power-management-independent embedded communications component. Key features include an integrated MAC and PHY, 8 KB of buffer RAM, an SPI host interface, 10BASE-T operation, and support for a 25 MHz parallel-resonance crystal. Its 28-pin SSOP package provides a relatively compact solution for embedded equipment. The -40°C to +85°C temperature range distinguishes the industrial-grade suffix from the standard ENC28J60/SS option. Because Ethernet magnetics, connectors, clocking, isolation, and careful board layout are still required, integration reduces host-side complexity without eliminating a complete network interface design. Technically, the ENC28J60-I/SS uses its integrated PHY to interface with 10BASE-T Ethernet while the MAC manages Ethernet frames and the host processor accesses device registers and packet data through SPI. The manufacturer datasheet states that the oscillator should operate at 25 MHz with a parallel-resonance crystal connected to OSC1 and OSC2; using a series-resonance crystal may produce a frequency outside the crystal manufacturer's specification. This clock detail is critical because SPI timing, Ethernet operation, and host communication depend on stable oscillator behavior. Typical applications include industrial automation controllers, embedded network gateways, environmental monitoring equipment, access-control terminals, building-automation nodes, and compact IoT devices. The controller is especially useful when a system already contains a microcontroller with SPI and only requires 10 Mb/s Ethernet rather than faster 100 Mb/s networking. Software support and PHY-level configuration remain part of the design because the host must service the controller and apply the required Ethernet termination and magnetics. Designers should reserve solid copper for the exposed thermal requirements of the SSOP, verify the oscillator network against the manufacturer guidance, and route the Ethernet differential pair as a controlled-impedance pair away from noisy switching circuits. The 3.1 V to 3.6 V operating range also requires a regulator with adequate transient margin for the indicated 180 mA supply current. Magnetic isolation and an RJ45-compatible transformer network remain external to this device. This product record combines manufacturer specifications, distributor pricing, verified package information, same-package alternatives, and practical integration guidance. It adds direct comparison and design notes that help distinguish a true pin-compatible substitution from devices that merely offer Ethernet connectivity through a different package or interface architecture.
ENC28J60/ML - 10BASE-T Ethernet Controller | Microchip
The Microchip ENC28J60/ML is a 28-pin standalone 10BASE-T Ethernet controller with an integrated MAC and PHY, 8 Kbytes of buffer RAM, and an SPI serial interface, supplied in a 28-QFN (6x6 mm) package. It connects a microcontroller to 10 Mbit/s Ethernet while handling packet buffering and physical-layer transmission, reducing host-side network hardware requirements. An Ethernet controller is an interface IC that connects a host processor to a physical network. In the ENC28J60 architecture, the MAC handles frame processing, the PHY handles 10BASE-T signaling, and the SPI interface communicates with the microcontroller. Unlike devices with an internal TCP/IP stack, the ENC28J60 requires the connected firmware to implement the higher-level network protocol. Key features include a 28-QFN (6x6 mm) package, integrated MAC and PHY, 8 Kbytes of buffer RAM, and an SPI interface. The manufacturer describes it as a compact solution intended to reduce board space, complexity, and cost. The device is suited to embedded systems that need an economical wired network connection rather than high-throughput Ethernet. The ENC28J60 is designed around a 25 MHz crystal oscillator connected between OSC1 and OSC2. Microchip specifically states that the design requires a parallel-resonance crystal and warns that a series-resonance crystal may produce an out-of-spec operating frequency. The SPI host interface and integrated PHY make the controller practical for small embedded control, monitoring, and data-acquisition equipment. Typical applications include industrial control nodes, building-automation terminals, environmental monitoring, remote instrumentation, embedded gateways, and low-bandwidth supervisory systems. Compared with larger SPI Ethernet controllers such as W5500, the ENC28J60 provides a smaller integrated solution but does not provide the same level of hardware-supported TCP/IP functionality. It is therefore most appropriate where firmware already contains the required network stack. A key design consideration is matching the crystal, decoupling, Ethernet magnetics, and PCB layout to the manufacturer recommendations. The 6x6 mm QFN package also requires careful assembly and land-pattern planning. Designers should verify the exact package, pinout, electrical limits, and temperature variant against the current Microchip datasheet before releasing a production PCB.
ENC28J60/SS - 10Mbps SPI Ethernet Controller | Microchip
The Microchip Technology ENC28J60/SS is a 10 Mbps stand-alone Ethernet controller with an integrated MAC, 10BASE-T PHY, 8 KB of buffer RAM, and an SPI serial interface in a 28-pin SSOP package. It operates from a 3.1 V to 3.6 V supply and supports an industrial temperature variant family identified by the ENC28J60-I/SS ordering code. What is a stand-alone Ethernet controller? It is an Ethernet interface integrated circuit that connects a host microcontroller or processor to a physical Ethernet network. The ENC28J60/SS combines MAC and PHY functions with packet buffering, while the host communicates through SPI rather than a parallel bus. Its 10 Mbps 10BASE-T capability makes it suitable for legacy and low-bandwidth embedded networks, especially where board area and system cost are important. Key verified features include 10 Mbps Ethernet operation, integrated MAC and PHY, 8 KB of buffer RAM, SPI interface, a 28-pin SSOP package, and a 3.1 V to 3.6 V supply range. The controller is designed to reduce host-side interface complexity and can be used in systems where the connected host already has sufficient processing capacity for the required networking software. The ENC28J60/SS includes the MAC and PHY in one package, allowing an embedded system to implement Ethernet communication without a separate external Ethernet PHY. Its buffer RAM supports packet handling between the SPI host interface and the Ethernet physical layer. The manufacturer product page identifies it as a 28-pin 10BASE-T stand-alone Ethernet controller with 8 Kbytes of buffer RAM. Typical applications include embedded control systems, industrial automation equipment, data loggers, building automation controllers, network-connected sensors, and microcontroller platforms requiring 10BASE-T connectivity. The SPI interface allows the device to be paired with host controllers such as STM32, ATmega, PIC, or other embedded processors that provide the required firmware. When designing around the ENC28J60/SS, confirm the 3.1 V to 3.6 V operating supply, use the manufacturer-recommended 25 MHz parallel-resonance crystal arrangement, and provide the required magnetic-interface and Ethernet physical-layer components. Verify the exact SSOP footprint, pin assignment, thermal conditions, and host timing requirements against the manufacturer datasheet before layout release.
ENC28J60T/ML - 10Mbps SPI Ethernet Controller | Microchip
The Microchip Technology ENC28J60T/ML is a 28-pin, 10Mbps stand-alone Ethernet controller with an integrated MAC and 10BASE-T PHY, an 8 Kbyte packet buffer, and an SPI serial interface in a 28-VQFN exposed-pad package. It operates from a 3.1 V to 3.6 V supply and is designed to add Ethernet connectivity to microcontrollers, programmable controllers, and other embedded systems equipped with SPI. An Ethernet controller is an interface IC that manages the lower-level tasks required for a host processor to communicate over an Ethernet network. Within the product hierarchy, the ENC28J60 is a stand-alone Ethernet controller, a network interface controller with integrated media-access control and physical-layer functions. Its combination of an SPI host interface and integrated 10BASE-T PHY reduces the number of external network-interface components required by an embedded design. Key features include IEEE 802.3-compatible Ethernet operation, 10Mbps networking, an integrated MAC and 10BASE-T PHY, and 8 Kbytes of transmit and receive packet-buffer SRAM. The SPI interface allows register and buffer access from a host controller. The device is supplied in a compact 28-VQFN package with an exposed pad, making it suitable for space-constrained embedded equipment where soldered surface-mount construction is preferred. The ENC28J60 architecture places the Ethernet MAC and PHY inside one package while retaining packet storage on the controller. This allows a host microcontroller to exchange Ethernet frames through SPI without implementing the complete Ethernet physical and data-link layers itself. According to the Microchip ENC28J60 documentation, the controller meets the relevant IEEE 802.3 requirements for 10BASE-T operation and supports both transmission and reception through the integrated packet buffer. Typical applications include industrial monitoring equipment, building-automation endpoints, environmental sensors, connected control systems, and compact embedded gateways. The controller is particularly useful when the host processor needs only 10BASE-T connectivity and has limited I/O or processing capacity. SPI-based register access also makes the ENC28J60 practical for platforms where parallel host buses would consume too many pins. Designers should provide a compliant 3.3 V supply, adequate 10BASE-T magnetic-interface components, and layout that minimizes Ethernet signal integrity and EMI issues. The exposed thermal pad requires suitable PCB copper and thermal-via treatment. Firmware must also handle ENC28J60 initialization, interrupt servicing, descriptor management, and network-driver behavior rather than treating the controller as a protocol-independent plug-in peripheral. This page consolidates verified manufacturer and distributor information, package details, sourcing data, and replacement guidance. It also separates true same-footprint candidates from cross-package Ethernet alternatives so engineers can evaluate PCB compatibility before making a design change.