PIC32MX795F512H-80V/PT : MCU MIPS 32 bits avec USB-OTG, Ethernet et double CAN — caractéristiques, brochage, alternatives et approvisionnement (2026)

Quick Answers: PIC32MX795F512H-80V/PT At a Glance

The PIC32MX795F512H-80V/PT from Microchip Technology is a 32-bit MIPS M4K microcontroller integrating 80 MHz / 105 DMIPS compute, 512 KB Flash, 128 KB SRAM, USB 2.0 On-The-Go with on-chip PHY, 10/100 Ethernet MAC (MII/RMII), and dual CAN 2.0b controllers with 1024 message buffers in a 64-pin TQFP package. Operating from 2.3 V to 3.6 V across -40 °C to +105 °C, it is the highest-integration member of the PIC32MX5XX/6XX/7XX family and the strongest fit for industrial Ethernet gateways, USB-OTG peripherals, dual-CAN industrial nodes, and QVGA HMI controllers. The part is in active production: verified distributor pricing starts at $7.45 per unit at ≥ 1000 pieces and $11.20 at single-unit (as of 2026-10-06), with multi-thousand-unit stock listed at authorized distributors. View the live product page on XAIPART for tier pricing and lead times.

This pillar consolidates the Microchip family datasheet (document 61156G) with the verified XAIPART product database to give engineers a single-source reference for selection, design-in, alternatives, and sourcing of the PIC32MX795F512H-80V/PT.

Technical Guide: How do you design in the PIC32MX795F512H-80V/PT?

The PIC32MX795F512H-80V/PT is a single-chip connected MCU: CPU, Flash, SRAM, USB-OTG PHY, Ethernet MAC, dual CAN, and 8 DMA channels all sit on one die. The design-in effort shifts from inter-chip glue logic to power integrity, PHY selection, and impedance-controlled routing.

Power architecture

The device operates from a single 2.3 V to 3.6 V rail (verified) with a dedicated VDDUSB pin powering the on-chip USB transceiver. VDDUSB (pin 56) should be tied to the same 3.3 V regulated rail as the main VDD pins, each with its own 10 µF bulk + 0.1 µF ceramic decoupling pair placed within 5 mm of the respective pin. Per the family datasheet, the 80 MHz speed grade requires VDD ≥ 2.5 V to maintain the rated 105 DMIPS throughput. Designs that need to retain RAM contents in Sleep should verify their brown-out and POR thresholds against the datasheet electrical-characteristics tables. Designers targeting battery-backed edge nodes should plan around the datasheet's documented Sleep, Idle, and Deep Sleep modes plus the fail-safe clock monitor.

Clock, reset, and JTAG/debug

The primary oscillator uses OSC1 (pin 9) and OSC2 (pin 10) and accepts a fundamental-mode crystal or ceramic resonator. MCLR (pin 11) is the master-clear reset input, active low, and requires a pull-up plus a 100 nF decoupling cap per datasheet recommendations. JTAG programming and on-chip debugging use TCK (pin 3), TDO (pin 4), TDI (pin 5), TMS (pin 6), and TRST (pin 13); the 4-wire JTAG plus TRST matches the standard Microchip programmer pinout used by MPLAB tools. The internal fail-safe clock monitor detects primary-oscillator faults and switches the system clock to the internal RC source for continued operation.

USB-OTG routing

The integrated USB 2.0 On-The-Go controller includes the on-chip PHY, so external components are limited to the 15 kΩ pull-down on D- (pin 58), the software-controlled 1.5 kΩ pull-up on D+ (pin 59), and the USBID resistor on pin 55 to select host or device role. Because the PHY is internal, no 24 MHz crystal is dedicated to USB; the main system oscillator feeds both the CPU and USB PLL. Full-speed (12 Mbps) and low-speed (1.5 Mbps) operation are supported per the verified application data. Keep D+/D- as a 90 Ω differential pair matched within 2 mm and avoid stubs.

Ethernet MAC and external PHY

The 10/100 Ethernet MAC supports both MII and RMII but requires an external PHY such as a Microchip KSZ8041 or a Texas Instruments DP83848 (both referenced in the verified FAQ). RMII reduces the MII data bus from 16 to 8 pins and is preferred when board real estate is tight; MII gives a broader PHY selection. Both modes need a reference clock — 50 MHz for RMII, 25 MHz for MII — typically sourced from the PHY and fed back into the MCU. Trace the Ethernet TX/RX pairs (ETXD0 pin 60, ETXD1 pin 61, ECRS pin 62, ERXDV pin 63, ECOL pin 64) as 50 Ω single-ended controlled-impedance traces and place the PHY within 50 mm of the RJ-45 magnetics to meet standard 10/100 Ethernet signal-integrity requirements.

CAN and DMA offload

Two independent CAN 2.0b controllers each have 1024 message buffers per the verified database record. Eight DMA channels (verified) service USB, Ethernet, and CAN in parallel. This offload is critical for deterministic latency: at 1 Mbit/s CAN traffic, polling would consume a significant share of the 80 MHz core. The DMA-driven architecture keeps CAN response times in the tens of microseconds even while Ethernet packets stream in the background.

Parallel Master Port for HMI displays

The 16-bit PMP on pins PMD0 through PMD15 (verified, port-B pins 28-41 and 44-47) addresses QVGA (320×240) TFT panels without an external graphics controller, sharing pins with GPIO port B. Combined with 128 KB of internal SRAM (verified), the MCU can buffer a full QVGA frame internally — no external SDRAM required for cost-sensitive industrial HMIs. The PMP supports both Intel 8080 and Motorola 6800 modes plus dedicated control lines for chip-select, read-strobe, and write-strobe.

Analog, serial, and timers

A 16-channel 10-bit ADC at 1 Msps covers sensor inputs across the analog-capable pins; two I²C ports, two SPI ports, and five UART modules round out the peripheral mix. The 51 GPIO (verified) include the 16 PMP data lines plus all control and analog pins, leaving room for keypad scanning, status LEDs, and auxiliary I/O. The PPS (Peripheral Pin Select) peripheral allows most digital functions to be remapped to alternative pins without re-routing.

Thermal, PCB layout, and unused pins

The 'V' suffix denotes -40 °C to +105 °C industrial operation. In a still-air enclosure near heat sources (motor drives, regulators), derate the TQFP-64 θJA per the datasheet and add a top-layer copper pour under the exposed pad area. Unused pins should be configured as outputs driving low, or as inputs with the internal pull-up enabled, to minimize Sleep-mode current. Pin 1 (RPB5/PMD5/RF1) is multifunction; with PPS, the same physical pin can be remapped to UART, SPI, or other peripheral roles without re-routing.

Engineering takeaway: the PIC32MX795F512H-80V/PT collapses a CPU + USB-PHY chip + Ethernet controller + dual CAN controller into one 64-pin TQFP; design effort shifts from inter-chip glue to PHY selection, impedance-controlled routing, and JTAG access.

Alternatives & Comparison: Which PIC32MX parts are drop-in compatible?

The PIC32MX family offers multiple pin-compatible alternatives within the 64-pin TQFP footprint. The table below uses only verified specs from the XAIPART product database; each row is a direct comparison of the verified product data, not an estimate.

For an exact die match in tape-and-reel packaging, the PIC32MX795F512H-80V/PT with -ND suffix is electrically identical (verified). For a smaller footprint, the PIC32MX795F512H-80V/MR ships in QFN-64 (9×9 mm) but requires a PCB land-pattern change — not a true drop-in. For step-down migration within the same footprint when Ethernet is unused, the PIC32MX575F512H-80V/PT is the lowest-cost pin-compatible option at verified spec parity for Flash and speed. The PIC32MX775F512H-80V/PT matches the MX795 for Ethernet and USB-OTG but lacks the dual CAN modules, making it a drop-in if the design only needs one CAN bus.

Engineering takeaway: the only true drop-in alternatives inside the 64-pin TQFP footprint are the 'I' temperature variant and the ND packaging code; all other variants either drop a peripheral (CAN, Ethernet) or change the package (MR = QFN).

Industry Insight: Where does the PIC32MX795F512H-80V/PT sit in the 2026 connected-MCU market?

The PIC32MX795F512H-80V/PT is in active production with no EOL announcement from Microchip (verified lifecycle status: active). Stock at major distributors is multi-thousand-unit and the part is not allocated as of 2026-10-06. Verified distributor pricing spans $11.20 at single-unit down to $7.45 at ≥ 1000 pieces, with tier breaks at 10 ($10.05), 100 ($8.95), 500 ($8.10), and 1000 ($7.45) units per the database pricing record.

From a market-segment view, the PIC32MX family occupies the connectivity-heavy tier between Microchip's 16-bit PIC24/dsPIC DSC line and the higher-performance PIC32MZ series. Within the PIC32MX5XX/6XX/7XX sub-family, the '7' suffix (MX7xx) is the only tier combining USB-OTG with on-chip PHY, Ethernet MAC, and dual CAN 2.0b in a single part — making this the de facto reference MCU for industrial Ethernet/IP gateways, CANopen nodes, and USB-OTG peripherals that previously required a discrete MCU plus three separate peripheral controllers.

For the OEM sourcing engineer, the key indicators to track are: (1) Microchip's product-change-notification feed for any pin-compatible die shrink, (2) distribution stock at major authorized channels (currently well-stocked per the verified data), and (3) the price trend at the 1000-piece break (currently $7.45 per the database). Lead time is stock to 4 weeks at major distributors as of the same data snapshot, with Microchip Direct factory-direct volumes running 8-12 weeks from order acknowledgment.

Engineering takeaway: in 2026 the PIC32MX795F512H-80V/PT is a mature, actively-produced part with stable pricing and healthy distributor stock — a safe BOM choice for industrial designs with a 5-7 year production horizon. For the wider category, the XAIPART component catalog lists comparable 32-bit MCUs across manufacturers if a second-source evaluation is required.

Trends & Outlook: What should buyers watch over the next 18-24 months?

Three trends, each anchored to verified data points, shape the near-term outlook for this MCU.

1. Migration pressure from PIC32MZ EF. The PIC32MZ EF series delivers higher DMIPS and more RAM, but it is not a drop-in replacement: software rework is required because the peripheral library and register map differ. Buyers evaluating a redesign should weigh the higher compute against the firmware porting cost. For new designs where 105 DMIPS is sufficient, the PIC32MX795F512H-80V/PT remains the lower-risk path; for designs that need hardware crypto or 200+ DMIPS, PIC32MZ is the upgrade.

2. Industrial Ethernet demand. With 10/100 Ethernet MAC, dual CAN, and 512 KB Flash, this MCU targets the converged industrial-network node — the device that bridges EtherNet/IP, PROFINET, Modbus TCP, and CANopen. As IT/OT convergence accelerates, parts that consolidate Ethernet + CAN + USB into one chip with industrial temperature grading have a structural demand tailwind. The 512 KB Flash budget (verified) accommodates a full TCP/IP stack plus CANopen or Modbus stack plus application logic in a single chip, eliminating the external memory that discrete multi-IC solutions require.

3. Sourcing risk and second-source. Microchip does not second-source the PIC32MX family, so any fab disruption at the parent wafer line is a single-point risk. Verified data shows the part is currently well-stocked and not allocated, but buyers with multi-year production should track the Microchip PCN feed and consider holding safety stock at the 1000-piece price break ($7.45 verified) rather than relying on spot orders. For broader context on Microchip 32-bit USB MCU options, the PIC32MX460F512L-80I/PT guide and the PIC32MX340F512H-80I/MR guide cover related parts in the same family.

For the design engineer, two practical rules follow: (a) lock the PCB to the 64-pin TQFP footprint so the 'I' temperature variant and ND packaging code remain interchangeable, and (b) use the PIC32MX795F512H-80V/PT only when the full peripheral mix is justified — for designs that don't need dual CAN or Ethernet, the pin-compatible PIC32MX575 or PIC32MX695 saves cost without redesign.

Engineering takeaway: the part is a stable, mature choice today; the real forward risk is design churn toward PIC32MZ, not supply disruption — so the most defensive strategy is to constrain the BOM to the verified peripheral mix and keep the TQFP-64 footprint compatible with cheaper variants. For additional reading on related PIC32 and PIC18 architectures, see the XAIPART blog index.