10AS057H4F34I3LG vs 10AS057K2F35E2LG Comparaison
Comparaison détaillée côte à côte de 10AS057H4F34I3LG par Intel et 10AS057K2F35E2LG par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
10AS057H4F34I3LG - Arria 10 SX SoC FPGA, 570K LE, Dual ARM Cortex-A9 | Intel
10AS057H4F34I3LG ✓ ActifComparaison des spécifications
| Paramètre | 10AS057H4F34I3LG | 10AS057K2F35E2LG |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $2 280,00 | $3 450,00 |
| Product Type | SoC FPGA (System-on-Chip FPGA) | — |
| Series | Arria 10 SX | — |
| Family | 10AS057 | Arria 10 SX SoC FPGA |
| Logic Elements | 570,000 | 570,000 |
| Process Technology | 20 nm | — |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum CPU Frequency | 1.5 GHz | — |
| Core Voltage | 0.9 V | — |
| Number of Logic Cells | 570,000 | — |
| Number of I/O | 492 | — |
| Boîtier | 1152-FBGA, FC (35x35 mm) | 1152-ball FCBGA, 35 mm x 35 mm, 1.0 mm pitch |
| Package Code | BGA, F34 | — |
| Type de montage | Surface Mount | — |
| Température de fonctionnement | -40C to +100C (Industrial) | -40C to +100C (extended-industrial screening) |
| Temperature Grade | Industrial | — |
| Statut RoHS | Compliant | Compliant |
| Supply Form | Tray | — |
| Architecture | FPGA + Hard Processor System (HPS) | — |
| Process Node | — | TSMC 20 nm |
| HPS Cores | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Max Frequency | — | 1.5 GHz |
| DSP Blocks | — | [DATA_NEEDED: 18x19 multiplier count] |
| Embedded Memory (M20K) | — | [DATA_NEEDED: M20K block count and total bits] |
| Transceivers | — | Up to 24 channels, up to 17.4 Gbps |
| PCIe Hard IP | — | Gen3 x4 (rootport/endpoint) |
| User I/Os | — | 396 |
| Speed Grade | — | E2 (commercial/extended) |
| Configuration | — | SRAM-based, partial reconfiguration, SEU mitigation, ECC |
| Memory Interfaces | — | DDR3/DDR4 with hard PHY (HPS + FPGA) |
| Lead-Free | — | Yes |