10AS057K2F35I1HG vs 10AS057K2F35E2LG Comparaison
Comparaison détaillée côte à côte de 10AS057K2F35I1HG par Intel et 10AS057K2F35E2LG par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 10AS057K2F35I1HG | 10AS057K2F35E2LG |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $3 820,00 | $3 450,00 |
| Device Family | Arria 10 SX SoC FPGA | — |
| Logic Elements | 570K | 570,000 |
| Processor Subsystem | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum Fabric Frequency | 1.5 GHz | — |
| User I/O Count | 396 | — |
| Boîtier | 1152-FBGA, FC (35x35 mm) | 1152-ball FCBGA, 35 mm x 35 mm, 1.0 mm pitch |
| Speed Grade | K2 (mid) | E2 (commercial/extended) |
| Temperature Grade | Industrial (I1: -40C to +100C) | — |
| Type de montage | Surface Mount (Flip-Chip BGA) | — |
| Process Node | 20 nm | TSMC 20 nm |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | [DATA_NEEDED: 18x19 multiplier count] |
| Embedded Memory | M20K blocks | — |
| Transceivers | [DATA_NEEDED: transceiver count and data rate] | Up to 24 channels, up to 17.4 Gbps |
| Hard Memory Controllers | DDR4 with hard PHY | — |
| PCIe Hard IP | PCI Express Gen3 | Gen3 x4 (rootport/endpoint) |
| Statut RoHS | Compliant | Compliant |
| Lead-Free | Yes | Yes |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Family | — | Arria 10 SX SoC FPGA |
| HPS Cores | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Max Frequency | — | 1.5 GHz |
| Embedded Memory (M20K) | — | [DATA_NEEDED: M20K block count and total bits] |
| User I/Os | — | 396 |
| Température de fonctionnement | — | -40C to +100C (extended-industrial screening) |
| Configuration | — | SRAM-based, partial reconfiguration, SEU mitigation, ECC |
| Memory Interfaces | — | DDR3/DDR4 with hard PHY (HPS + FPGA) |