10AS057K3F35I2SG vs 10AS057K2F35I2SG Comparaison
Comparaison détaillée côte à côte de 10AS057K3F35I2SG par Intel et 10AS057K2F35I2SG par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 10AS057K3F35I2SG | 10AS057K2F35I2SG |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $2 853,32 | $3 198,40 |
| Family | Arria 10 SX | Arria 10 SX SoC FPGA |
| Device Variant | 10AS057 | — |
| Logic Elements | 570K | 570K |
| HPS Core | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 1.5 GHz | — |
| User I/O Count | 396 | 396 (per Heisener parametric data) |
| Boîtier | 1152-FBGA, FC (35x35 mm) | 1152-ball FC-FBGA (F35), 35x35 mm |
| Speed Grade | K3 | -2 |
| Température de fonctionnement | -40C to +100C (Industrial, I2) | -40C to +100C (Industrial) |
| Process Technology | 20nm | — |
| Memory Controller | Hard DDR3/4 controller in HPS and FPGA fabric | — |
| Transceivers | Multi-gigabit transceivers (per Arria 10 SX family datasheet) | [DATA_NEEDED: transceiver count and max data rate] |
| Type de montage | Surface Mount (Flip-Chip BGA) | Surface Mount (BGA) |
| Statut RoHS | Compliant (per Altera product page) | Compliant (lead-free finish) |
| Product Type | SoC FPGA - Embedded System on Chip | — |
| Processor Core | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Core Frequency | — | 1.5 GHz |
| Process Node | — | 20 nm TSMC |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Embedded Memory | — | [DATA_NEEDED: M20K / MLAB bit count] |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, SPI, I2C, NAND/NOR flash controllers, SD/MMC |
| Memory Interfaces | — | DDR3/DDR4/LPDDR3 hard controllers (Arria 10 HPS) |
| Configuration | — | FPGA + HPS independent / coordinated boot |
| Niveau MSL | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |