10AX090U1F45I1SG vs 10AX090U2F45I1SG Comparaison
Comparaison détaillée côte à côte de 10AX090U1F45I1SG par Intel et 10AX090U2F45I1SG par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 10AX090U1F45I1SG | 10AX090U2F45I1SG |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9 750,00 | $6 895,59 |
| Product Type | FPGA - Field Programmable Gate Array | — |
| Series | Arria 10 GX | Arria 10 GX |
| Logic Elements | 900,000 LE | 900,000 |
| Adaptive Logic Modules (ALMs) | 339,620 ALM | — |
| Embedded Memory | 47.32 Mbit | — |
| Number of I/O | 480 user I/O | — |
| Number of Terminals | 1932 balls | — |
| Boîtier / Format | 1932-BBGA, FCBGA | — |
| Package Code | BGA (Square) | — |
| Form of Terminal | Ball | — |
| Type de montage | Surface Mount | Surface Mount |
| Operating Temperature Grade | INDUSTRIAL | — |
| Process Technology | 20 nm | 20 nm Tri-Gate |
| Transceiver Speed | Up to 28.05 Gbps (per Arria 10 GX family) | — |
| Configuration | JTAG, Passive Serial, Active Serial | — |
| Hard IP | PCIe Gen3/Gen2 hard IP, variable-precision DSP, PLL | — |
| Packaging | Tray | — |
| Statut RoHS | Compliant | Compliant |
| Embedded Memory Bits | — | 59,234,304 bits |
| User I/Os | — | 480 |
| Boîtier | — | 1932-BBGA, FCBGA (45 mm x 45 mm) |
| Température de fonctionnement | — | -40C to +100C (Industrial) |
| Temperature Grade | — | I (Industrial) |
| Speed Grade | — | U2 |
| RoHS Version | — | SG suffix indicates RoHS-compliant |
| Transceivers | — | Up to 24 transceiver channels (family-level, [DATA_NEEDED: per-channel data rate confirmation]) |
| DSP Blocks | — | Variable-precision DSP blocks (family-level, [DATA_NEEDED: exact count for 10AX090]) |
| Hard Memory Controllers | — | Yes (DDR3/DDR4 with ECC, family-level) |