10AX090U3F45I2LG vs 10AX090U3F45E2LG Comparaison
Comparaison détaillée côte à côte de 10AX090U3F45I2LG par Intel et 10AX090U3F45E2LG par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 10AX090U3F45I2LG | 10AX090U3F45E2LG |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9 750,00 | $6 900,00 |
| Family | Arria 10 GX | — |
| Logic Elements | 900,000 | — |
| Embedded Memory | 59,234,304 bits (~7.4 MB) | — |
| User I/Os | 480 | — |
| Process Node | 20 nm | — |
| Core Voltage | 0.9 V | — |
| Operating Temperature Grade | Industrial (-40C to +100C) | OTHER / Extended (per Partstack listing) |
| Boîtier | 1932-ball FCBGA (FBGA) | 1932-BBGA, FCBGA |
| Number of Terminals | 1932 | — |
| Type de montage | Surface Mount (BGA) | — |
| Statut RoHS | Compliant | Compliant |
| Lead-Free | Yes | — |
| Hardened Transceivers | Yes (GX multi-gigabit) | — |
| PCI Express Hard IP | Gen3 (embedded) | — |
| DSP Blocks | Variable-precision DSP with hard floating point | [DATA_NEEDED: DSP block count] |
| Memory Controller Hard IP | DDR4/DDR3/LPDDR3 | — |
| Series | — | Arria 10 GX |
| Logic Elements (LE) | — | 900,000 |
| Number of Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Embedded Memory Bits | — | 59,234,304 bits |
| Number of Transceivers | — | 48 transceiver macro channels (480 I/O references) |
| Maximum Transceiver Data Rate | — | [DATA_NEEDED: exact Gbps] |
| Hard Memory Controllers | — | Yes - DDR4, DDR3, QDR IV, RLDRAM 3 with hardened PHY |
| Hard PCIe Controllers | — | PCIe Gen3 x8 |
| Hard Ethernet MACs | — | 10GbE and 100GbE MACs |
| Adaptive Logic Modules (ALMs) | — | [DATA_NEEDED: ALM count] |
| Number of I/O Banks | — | [DATA_NEEDED: bank count] |
| Maximum User I/O Pins | — | 480 (per DigiKey listing) |
| Package Pin Pitch | — | [DATA_NEEDED: pitch] |
| Process Technology | — | 20nm TSMC |
| Configuration Method | — | Serial (active/passive) and parallel via Quartus Prime |
| Development Tool | — | Intel Quartus Prime |