10AX115H2F34E2LG vs 10AX115H2F34I2SG Comparaison
Comparaison détaillée côte à côte de 10AX115H2F34E2LG par Intel et 10AX115H2F34I2SG par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
10AX115H2F34E2LG - Arria 10 GX FPGA 1.15M LE 1152-FCBGA | Intel / Altera
10AX115H2F34E2LG ✓ ActifAltera
10AX115H2F34I2SG - Arria 10 GX 1.15M Logic Elements FPGA | Altera | Intel
10AX115H2F34I2SG ✓ ActifComparaison des spécifications
| Paramètre | 10AX115H2F34E2LG | 10AX115H2F34I2SG |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $5 950,00 | $3 640,00 |
| Series | Arria 10 GX | — |
| Family | Arria 10 | Arria 10 GX |
| Logic Elements (LE) | 1,150,000 | — |
| Embedded Memory | 68,857,856 bits | 68.86 Mbit |
| User I/O Count | 504 | — |
| Core Voltage | 0.9 V | — |
| Process Technology | 20 nm | 20 nm Tri-Gate |
| Boîtier | 1152-BBGA, FCBGA | 1152-ball FC-FBGA (F34) |
| Type de montage | Surface Mount | Surface Mount |
| Number of Terminals | 1152 | — |
| Package Code | BGA | — |
| Package Shape | Square | — |
| Terminal Form | Ball | — |
| Operating Temperature Grade | Industrial (E2 = -40C to +100C) | — |
| Statut RoHS | Compliant | Compliant |
| Logic Elements | — | 1,150,000 |
| Adaptive Logic Modules (ALMs) | — | 427,200 |
| DSP Blocks | — | 1,518 (variable precision, hardened FP32) |
| Transceiver Channels | — | 24 (max up to 14.1 Gbps) |
| PCIe Hard IP | — | 2x PCIe Gen3 |
| User I/O Banks | — | [DATA_NEEDED: number of user I/O banks] |
| Maximum User I/Os | — | [DATA_NEEDED: maximum user I/O count] |
| Core Voltage (SmartVID) | — | 0.85 V to 0.9 V |
| Speed Grade | — | H2 |
| Temperature Grade | — | Industrial (I2, -40C to +100C Tj) |
| Lead-Free | — | Yes |
| Niveau MSL | — | [DATA_NEEDED: moisture sensitivity level] |