5CSEBA4U19C7SN vs 5CSEBA4U19C8N Comparaison
Comparaison détaillée côte à côte de 5CSEBA4U19C7SN par Intel et 5CSEBA4U19C8N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
5CSEBA4U19C8N - Cyclone V SE SoC FPGA, 40K LE, Dual ARM Cortex-A9 | Intel
5CSEBA4U19C8N ✓ ActifComparaison des spécifications
| Paramètre | 5CSEBA4U19C7SN | 5CSEBA4U19C8N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $218,00 | $54,75 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 40 K | 40K |
| Hard Processor System | Single ARM Cortex-A9 MPCore with CoreSight | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | 800 MHz | 600 MHz |
| Process Technology | 28 nm low-power | TSMC 28nm low-power |
| Core Voltage (FPGA fabric) | 1.1 V | — |
| Boîtier | 484-UBGA (UBGLA) 19x19 mm | 484-UBGA (19x19 mm) |
| Package Code | FBGA (U19) | — |
| User I/O (approx.) | 161 | — |
| I/O Standards | LVDS, LVCMOS, SSTL (1.0 V to 3.3 V) | — |
| Memory Controller | DDR3 / LPDDR2 hard controller | — |
| DSP Blocks | Variable-precision DSP blocks | [DATA_NEEDED: number of DSP blocks] |
| Configuration Modes | JTAG, AS, PS, FPP | — |
| Bitstream Encryption | AES (256-bit) | — |
| Température de fonctionnement | Commercial (0C to 85C, per 'C' suffix) | 0C to +85C (commercial) |
| Statut RoHS | Compliant | Compliant |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Niveau MSL | [DATA_NEEDED: MSL rating] | 3 (168 hours) |
| FPGA Fabric Speed Grade | — | -8 |
| User I/O Count | — | 161 |
| Lead-Free | — | Yes |
| Supply Voltage (Core) | — | [DATA_NEEDED: VCC core voltage] |
| Embedded Memory (M10K) | — | [DATA_NEEDED: M10K block count] |
| Transceivers | — | None (SE variant - no high-speed transceivers) |
| Configuration Method | — | Serial (EPCS) and Parallel |