5CSEBA4U19I7N vs 5CSEBA4U19I7SN Comparaison
Comparaison détaillée côte à côte de 5CSEBA4U19I7N par Altera et 5CSEBA4U19I7SN par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 5CSEBA4U19I7N | 5CSEBA4U19I7SN |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $72,00 | $145,00 |
| Family | Cyclone V SE SoC FPGA | — |
| Logic Elements | 40 K | 40,000 |
| Processor | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 800 MHz | 800 MHz |
| Boîtier | 484-UBGA (19x19 mm) | 484-pin UBG A (19x19 mm) |
| User I/O Pins | 240 | — |
| Operating Temperature Grade | Industrial (-40C to +100C) | — |
| Process Technology | 28 nm low-power | — |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Statut RoHS | Compliant | Compliant |
| Lead-Free | Yes | — |
| HPS Peripherals | USB 2.0, EMAC, NAND flash controller, DDR3 controller | — |
| I/O Standards | LVDS, LVTTL, LVCMOS | — |
| Speed Grade | I7 (industrial) | — |
| Series | — | Cyclone V SE SoC FPGA |
| Device Family | — | Cyclone V |
| Hard Processor System (HPS) | — | Single ARM Cortex-A9 MPCore with CoreSight |
| Température de fonctionnement | — | -40C to +100C (Industrial) |
| Process Node | — | 28 nm low-power |
| Supply Voltage (Core) | — | 1.1 V (typical) |
| I/O Standards Supported | — | LVTTL, LVCMOS, LVDS, SSTL, HSTL (Cyclone V I/O family) |
| Embedded Memory | — | [DATA_NEEDED: total Kbits of M9K blocks] |
| 18x18 Hardware Multipliers | — | [DATA_NEEDED: count] |
| PLLs | — | [DATA_NEEDED: count] |
| Transceivers | — | Not applicable (SE family, transceiver-less) |
| PCI Express Hard IP | — | Gen1 capable (rootport/endpoint) |
| DDR Memory Support | — | DDR2/DDR3/LPDDR2 via HPS and FPGA fabric |