5CSEBA4U23I7LN vs 5CSEBA6U23I7N Comparaison
Comparaison détaillée côte à côte de 5CSEBA4U23I7LN par Intel et 5CSEBA6U23I7N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 5CSEBA4U23I7LN | 5CSEBA6U23I7N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $99,75 | $51,80 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 40,000 | 110,000 |
| Processor Cores | Dual ARM Cortex-A9 MPCore | — |
| Processor Clock Speed | 925 MHz | — |
| Boîtier | 672-pin UBGA (23x23 mm) | 672-UBGA (UBG A-672) 23x23 mm |
| Température de fonctionnement | -40C to +100C (Industrial) | -40C to +100C (industrial, junction) |
| Type de montage | Surface Mount | — |
| Process Technology | 28nm TSMC low-power | 28 nm TSMC low-power |
| Embedded Memory | [DATA_NEEDED: exact embedded memory size in bits] | 5,662 Kbits (M10K + MLAB) |
| DSP Blocks (18x18 multipliers) | [DATA_NEEDED: exact multiplier count] | — |
| Transceivers | 3.125 Gbps (per Cyclone V family) | — |
| External Memory Interface | DDR3, DDR2, LPDDR2 (controller integrated in HPS + soft IP in FPGA fabric) | — |
| Niveau MSL | 3 | — |
| Statut RoHS | Compliant | — |
| Lead-Free | Yes | — |
| Sans halogène | [DATA_NEEDED] | — |
| Number of GPIOs | [DATA_NEEDED: per device variant] | — |
| Number of PLLs | [DATA_NEEDED: per device variant] | — |
| Hard Processor System | — | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 800 MHz |
| DSP Blocks | — | 224 (variable-precision) |
| Maximum User I/O | — | 364 |
| Core Voltage | — | 1.1 V |
| Speed Grade | — | 7 |
| Temperature Grade | — | Industrial (I) |
| Lead-Free / RoHS | — | Yes (Pb-free, N suffix) |
| DDR Controller | — | 32-bit DDR3/LPDDR2 with ECC |
| Configuration | — | FPGA + HPS integrated SoC |