5CSEBA5U19C7N vs 5CSEBA2U19I7N Comparaison
Comparaison détaillée côte à côte de 5CSEBA5U19C7N par Intel et 5CSEBA2U19I7N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 5CSEBA5U19C7N | 5CSEBA2U19I7N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $99,20 | $445,65 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 85,000 | 25K |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 800 MHz per core | — |
| Boîtier | 484-UBGA (UBGAmobile, 19x19 mm) | 484-UBGA (19x19 mm) |
| Température de fonctionnement | 0C to +85C (commercial, junction) | -40C to +100C (Industrial) |
| Speed Grade | -7 (standard) | — |
| Process Node | 28 nm low-power (TSMC) | — |
| Supply Voltage (Core) | 1.1 V typical | — |
| DSP Blocks | Variable-precision, 18x18 / 27x27 multipliers | — |
| Embedded Memory | M10K + MLAB blocks, ~4,450 Kbits total | 1,400 Kbits |
| HPS Peripherals | EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART | — |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| RoHS / Pb-free | Yes | — |
| Configuration Memory | External (active serial via HPS or FPGA) | — |
| Niveau MSL | 3 (per JEDEC J-STD-020, reflow 260C) | — |
| Block Pins (User I/O) | Approximately 66 user I/O pins | — |
| HPS | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Clock Frequency | — | 800 MHz |
| DSP Blocks (18x18 Multipliers) | — | 66 |
| User I/O Pins | — | 145 |
| LVDS Support | — | Up to 1.25 Gbps |
| Process Technology | — | 28 nm TSMC low-power |
| Voltage - Input (Max) | — | 1.1 V core |
| Peripherals | — | USB 2.0 OTG, Gigabit Ethernet, CAN, UART, SPI, I2C, NAND/NOR flash controllers |
| HPS-FPGA Interconnect | — | AXI bridges (3 master / 3 slave), FPGA-to-HPS SDRAM, DMA |
| Statut RoHS | — | Compliant |