5CSEBA6U19A7N vs 5CSEBA5U19C7N Comparaison
Comparaison détaillée côte à côte de 5CSEBA6U19A7N par Intel et 5CSEBA5U19C7N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 5CSEBA6U19A7N | 5CSEBA5U19C7N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $198,40 | $99,20 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Device Variant | 5CSEA6 (U19) | — |
| Logic Elements | 110,000 | 85,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Clock Frequency | 700 MHz | — |
| Core Voltage | 1.1 V | — |
| Boîtier | 484-pin UBGFA / UFBGA (19x19 mm) | 484-UBGA (UBGAmobile, 19x19 mm) |
| Operating Temperature Grade | Automotive AEC-Q100 | — |
| Supply Form | Tray | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| FPGA Architecture | SRAM-based, low-power process | — |
| Memory Blocks | M10K + MLAB embedded memory | — |
| DSP Blocks | Variable-precision DSP | Variable-precision, 18x18 / 27x27 multipliers |
| Peripherals | EMAC, USB, CAN, SPI, I2C, UART, NAND/NOR flash, DDR3 controller with ECC | — |
| Statut RoHS | Compliant | — |
| HPS Maximum Frequency | — | 800 MHz per core |
| Température de fonctionnement | — | 0C to +85C (commercial, junction) |
| Speed Grade | — | -7 (standard) |
| Process Node | — | 28 nm low-power (TSMC) |
| Supply Voltage (Core) | — | 1.1 V typical |
| Embedded Memory | — | M10K + MLAB blocks, ~4,450 Kbits total |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART |
| RoHS / Pb-free | — | Yes |
| Configuration Memory | — | External (active serial via HPS or FPGA) |
| Niveau MSL | — | 3 (per JEDEC J-STD-020, reflow 260C) |
| Block Pins (User I/O) | — | Approximately 66 user I/O pins |