5CSEBA6U19C7SN vs 5CSEBA5U19I7SN Comparaison
Comparaison détaillée côte à côte de 5CSEBA6U19C7SN par Intel et 5CSEBA5U19I7SN par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 5CSEBA6U19C7SN | 5CSEBA5U19I7SN |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $149,85 | $118,40 |
| Series | Cyclone V SE SoC FPGA | — |
| Family | 5CSEBA6 (Cyclone V SE, 110K LE) | Cyclone V SE SoC FPGA |
| Logic Elements | 110,000 | 85K |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | Single-core ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Clock Frequency | 800 MHz | — |
| User I/O Pins | 66 (FPGA fabric, per distributor listing) | — |
| Total Package Pins | 484 | — |
| Package Type | 484-UBGA (Ultra BGA), 19x19 mm | — |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Température de fonctionnement | Industrial grade (per part number code) | — |
| Statut RoHS | Compliant | Compliant |
| Lead-Free | Yes | — |
| FPGA Process Node | Low-power TSMC process | — |
| On-Chip Memory | Embedded SRAM (FPGA fabric) | — |
| DSP Blocks | Variable-precision DSP blocks (Cyclone V architecture) | [DATA_NEEDED: DSP block count for 5CSEA5] |
| Transceivers | Not enabled on this SE variant | [DATA_NEEDED: transceiver count for 5CSEA5 U19] |
| Device Variant | — | 5CSEA5 |
| HPS Maximum Clock | — | 800 MHz |
| FPGA Fabric Maximum Clock | — | [DATA_NEEDED: maximum fabric frequency] |
| Boîtier | — | 484-pin UBG (Ultra FineLine BGA, 19x19 mm) |
| Package Designator | — | U19 |
| Speed/Logic Grade | — | A5 (mid-tier speed grade) |
| User I/O Count | — | 66 (per distributor listing); up to 288 in Cyclone V SE family typical |
| Embedded Memory | — | [DATA_NEEDED: total Kbits] |
| PLL Count | — | [DATA_NEEDED: PLL count for 5CSEA5] |
| Température de jonction en fonctionnement | — | -40C to +100C (industrial) |
| Process Technology | — | TSMC 28 nm low-power |
| Configuration | — | SRAM-based, volatile |
| Niveau MSL | — | [DATA_NEEDED: moisture sensitivity level] |