5CSXFC4C6U23C8N vs 5CSXFC6C6U23C8N Comparaison
Comparaison détaillée côte à côte de 5CSXFC4C6U23C8N par Intel et 5CSXFC6C6U23C8N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
5CSXFC6C6U23C8N - Cyclone V SX SoC FPGA, 110K LE, ARM Cortex-A9 | Intel
5CSXFC6C6U23C8N ✓ ActifComparaison des spécifications
| Paramètre | 5CSXFC4C6U23C8N | 5CSXFC6C6U23C8N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $90,00 | $445,00 |
| Family | Cyclone V SX SoC FPGA | Cyclone V SX (SoC FPGA) |
| Series | Cyclone V SX | Cyclone V SX |
| Architecture | MCU + FPGA (Hard Processor System + Programmable Logic) | MCU + FPGA (Hard Processor System + FPGA fabric) |
| Hard Processor System (HPS) | Dual ARM Cortex-A9 MPCore with CoreSight | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Clock Frequency | 600 MHz | — |
| Logic Elements | 40,000 | 110,000 |
| User I/Os | 224 | — |
| Total I/O Count (per digchip) | 224 | — |
| Boîtier | 672-UBGA (23x23 mm) | 672-pin UFBGA (UBGA), 23x23 mm |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Packaging | Tray | — |
| Operating Temperature Grade | Industrial (per device suffix 8) | — |
| Process Technology | TSMC 28 nm low-power | 28 nm low-power (TSMC) |
| On-chip Memory | M9K memory blocks | — |
| DSP Blocks | Variable-precision DSP | Variable-precision DSP (number not specified in retrieved data) |
| Transceivers | Integrated high-speed transceivers | Up to 3.125 Gbps integrated transceivers |
| Statut RoHS | Compliant | Compliant |
| Export Control | May require additional documentation to export from the United States | — |
| Core Voltage | — | 1.1 V |
| Processor Maximum Frequency | — | 600 MHz |
| HPS L1 Cache | — | 32 KB instruction + 32 KB data per core |
| HPS L2 Cache | — | 512 KB shared |
| Embedded Memory | — | M10K blocks (total Kbits [DATA_NEEDED: total embedded memory Kbits]) |
| Maximum User I/O | — | 145 user I/O (per DigChip summary; full count per package [DATA_NEEDED: package pinout max user I/O]) |
| Memory Controller | — | Hard controller supporting DDR2, DDR3, LPDDR2 |
| Température de fonctionnement | — | -40C to +100C (industrial grade, code C) |
| Niveau MSL | — | 3 (per JEDEC J-STD-020, typical for large BGA) |
| Lead-Free / Halogen-Free | — | Yes (lead-free BGA; halogen status [DATA_NEEDED: halogen-free yes/no]) |
| Speed Grade | — | C8 (commercial speed grade 8) |
| Lifecycle | — | Active (Cyclone V family in production) |