5CSXFC4C6U23C8N vs 5CSXFC6D6F31A7N Comparaison
Comparaison détaillée côte à côte de 5CSXFC4C6U23C8N par Intel et 5CSXFC6D6F31A7N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 5CSXFC4C6U23C8N | 5CSXFC6D6F31A7N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $90,00 | $345,50 |
| Family | Cyclone V SX SoC FPGA | Cyclone V SX SoC FPGA |
| Series | Cyclone V SX | — |
| Architecture | MCU + FPGA (Hard Processor System + Programmable Logic) | — |
| Hard Processor System (HPS) | Dual ARM Cortex-A9 MPCore with CoreSight | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Clock Frequency | 600 MHz | — |
| Logic Elements | 40,000 | 110,000 |
| User I/Os | 224 | — |
| Total I/O Count (per digchip) | 224 | — |
| Boîtier | 672-UBGA (23x23 mm) | 896-ball FBGA (31 x 31 mm) |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Packaging | Tray | — |
| Operating Temperature Grade | Industrial (per device suffix 8) | Automotive / AEC-Q100 |
| Process Technology | TSMC 28 nm low-power | 28 nm TSMC low-power |
| On-chip Memory | M9K memory blocks | — |
| DSP Blocks | Variable-precision DSP | Up to 224 (18 x 18 multipliers) |
| Transceivers | Integrated high-speed transceivers | — |
| Statut RoHS | Compliant | Compliant |
| Export Control | May require additional documentation to export from the United States | — |
| Maximum HPS Clock Frequency | — | 700 MHz |
| Core Voltage | — | 1.1 V |
| User I/O Count | — | 288 |
| Automotive Qualification | — | AEC-Q100 |
| Embedded Memory | — | Approximately 5.5 Mbits (M10K + MLAB) |
| Hard Memory Controller | — | DDR2 / DDR3 / LPDDR2 / QDR II+ |
| Hard IP Peripherals | — | PCIe Gen2, GbE, USB 2.0 OTG, NAND, SD/MMC |
| Configuration | — | FPGA + HPS subsystem, integrated |
| Niveau de sensibilité à l'humidité (MSL) | — | [DATA_NEEDED: MSL level] |