5CSXFC6C6U23A7N vs 5CSXFC6C6U23I7LN Comparaison
Comparaison détaillée côte à côte de 5CSXFC6C6U23A7N par Intel et 5CSXFC6C6U23I7LN par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 5CSXFC6C6U23A7N | 5CSXFC6C6U23I7LN |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $328,75 | $119,55 |
| Family | Cyclone V SX SoC FPGA | Cyclone V SX SoC FPGA |
| Logic Elements | 110,000 | 110K |
| Processor Subsystem | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Embedded Memory (M20K) | 5,140 Kbit | — |
| DSP Blocks (18x18) | 224 | — |
| Maximum User I/O | 364 LVDS-capable pins | — |
| Transceivers | 6 (up to 3.125 Gbps) | Integrated high-speed transceivers |
| Boîtier | 672-pin UBGAFBGA (23 x 23 mm) | 672-UBGA (23x23 mm) |
| Process Technology | TSMC 28 nm Low Power | 28 nm low-power |
| Core Voltage | 1.1 V | — |
| Hard Memory Controller | DDR2 / DDR3 / LPDDR2 with ECC | — |
| HPS Clock Frequency | Up to 925 MHz (per Cyclone V device datasheet) | — |
| Température de fonctionnement | Automotive grade (per part number decode A) | -40C to +100C (Industrial) |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Statut RoHS | Compliant (per Intel product page) | Compliant |
| Niveau MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Device Variant | — | 5CSXFC6C6U23 |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum HPS Clock Frequency | — | 925 MHz |
| Embedded Memory | — | [DATA_NEEDED: total Kbits] |
| DSP Blocks | — | Variable-precision, supports 18x18 and 27x27 multipliers |
| HPS Peripherals | — | USB, GbE, SD/SDIO/MMC, UART, SPI, I2C |
| Memory Interfaces | — | DDR3, DDR2, LPDDR2 |
| I/O Standards | — | LVDS, LVCMOS, SSTL |
| Configuration | — | HPS boot from NAND/NOR/SD/eMMC; FPGA via Quartus Prime |