5CSXFC6C6U23C7N vs 5CSXFC6C6U23C8N Comparaison
Comparaison détaillée côte à côte de 5CSXFC6C6U23C7N par Intel et 5CSXFC6C6U23C8N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
5CSXFC6C6U23C8N - Cyclone V SX SoC FPGA, 110K LE, ARM Cortex-A9 | Intel
5CSXFC6C6U23C8N ✓ ActifComparaison des spécifications
| Paramètre | 5CSXFC6C6U23C7N | 5CSXFC6C6U23C8N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $215,80 | $445,00 |
| Family | Cyclone V SX SoC FPGA | Cyclone V SX (SoC FPGA) |
| Logic Elements | 110,000 | 110,000 |
| Hard Processor Cores | Dual ARM Cortex-A9 MPCore | — |
| Processor Max Frequency | 800 MHz | — |
| Embedded Memory | 5,140 Kbits | M10K blocks (total Kbits [DATA_NEEDED: total embedded memory Kbits]) |
| 18x18 Multipliers | 224 | — |
| Transceivers | 6 (up to 3.125 Gbps) | Up to 3.125 Gbps integrated transceivers |
| User I/O Pins | 145 | — |
| Boîtier | 672-UBGA (23x23 mm) | 672-pin UFBGA (UBGA), 23x23 mm |
| Speed Grade | -7 (fastest) | C8 (commercial speed grade 8) |
| Température de fonctionnement | 0C to 85C (commercial) | -40C to +100C (industrial grade, code C) |
| Process Technology | 28 nm low-power | 28 nm low-power (TSMC) |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Niveau MSL | [DATA_NEEDED: MSL level] | 3 (per JEDEC J-STD-020, typical for large BGA) |
| Statut RoHS | Compliant | Compliant |
| Hard Cache (L2 shared) | 512 KB | — |
| Series | — | Cyclone V SX |
| Architecture | — | MCU + FPGA (Hard Processor System + FPGA fabric) |
| Core Voltage | — | 1.1 V |
| Hard Processor System (HPS) | — | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| Processor Maximum Frequency | — | 600 MHz |
| HPS L1 Cache | — | 32 KB instruction + 32 KB data per core |
| HPS L2 Cache | — | 512 KB shared |
| DSP Blocks | — | Variable-precision DSP (number not specified in retrieved data) |
| Maximum User I/O | — | 145 user I/O (per DigChip summary; full count per package [DATA_NEEDED: package pinout max user I/O]) |
| Memory Controller | — | Hard controller supporting DDR2, DDR3, LPDDR2 |
| Lead-Free / Halogen-Free | — | Yes (lead-free BGA; halogen status [DATA_NEEDED: halogen-free yes/no]) |
| Lifecycle | — | Active (Cyclone V family in production) |