5CSXFC6C6U23I7LN vs 5CSXFC6C6U23C8N Comparaison
Comparaison détaillée côte à côte de 5CSXFC6C6U23I7LN par Altera et 5CSXFC6C6U23C8N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
5CSXFC6C6U23C8N - Cyclone V SX SoC FPGA, 110K LE, ARM Cortex-A9 | Intel
5CSXFC6C6U23C8N ✓ ActifComparaison des spécifications
| Paramètre | 5CSXFC6C6U23I7LN | 5CSXFC6C6U23C8N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $119,55 | $445,00 |
| Family | Cyclone V SX SoC FPGA | Cyclone V SX (SoC FPGA) |
| Device Variant | 5CSXFC6C6U23 | — |
| Logic Elements | 110K | 110,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum HPS Clock Frequency | 925 MHz | — |
| Boîtier | 672-UBGA (23x23 mm) | 672-pin UFBGA (UBGA), 23x23 mm |
| Température de fonctionnement | -40C to +100C (Industrial) | -40C to +100C (industrial grade, code C) |
| Process Technology | 28 nm low-power | 28 nm low-power (TSMC) |
| Embedded Memory | [DATA_NEEDED: total Kbits] | M10K blocks (total Kbits [DATA_NEEDED: total embedded memory Kbits]) |
| DSP Blocks | Variable-precision, supports 18x18 and 27x27 multipliers | Variable-precision DSP (number not specified in retrieved data) |
| Transceivers | Integrated high-speed transceivers | Up to 3.125 Gbps integrated transceivers |
| HPS Peripherals | USB, GbE, SD/SDIO/MMC, UART, SPI, I2C | — |
| Memory Interfaces | DDR3, DDR2, LPDDR2 | — |
| I/O Standards | LVDS, LVCMOS, SSTL | — |
| Configuration | HPS boot from NAND/NOR/SD/eMMC; FPGA via Quartus Prime | — |
| Statut RoHS | Compliant | Compliant |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Series | — | Cyclone V SX |
| Architecture | — | MCU + FPGA (Hard Processor System + FPGA fabric) |
| Core Voltage | — | 1.1 V |
| Hard Processor System (HPS) | — | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| Processor Maximum Frequency | — | 600 MHz |
| HPS L1 Cache | — | 32 KB instruction + 32 KB data per core |
| HPS L2 Cache | — | 512 KB shared |
| Maximum User I/O | — | 145 user I/O (per DigChip summary; full count per package [DATA_NEEDED: package pinout max user I/O]) |
| Memory Controller | — | Hard controller supporting DDR2, DDR3, LPDDR2 |
| Niveau MSL | — | 3 (per JEDEC J-STD-020, typical for large BGA) |
| Lead-Free / Halogen-Free | — | Yes (lead-free BGA; halogen status [DATA_NEEDED: halogen-free yes/no]) |
| Speed Grade | — | C8 (commercial speed grade 8) |
| Lifecycle | — | Active (Cyclone V family in production) |