5M1270ZT144C5N vs 5M1270ZT144I5N Comparaison
Comparaison détaillée côte à côte de 5M1270ZT144C5N par Altera et 5M1270ZT144I5N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ ActifComparaison des spécifications
| Paramètre | 5M1270ZT144C5N | 5M1270ZT144I5N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $12,45 | $17,90 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Series | MAX V | — |
| Logic Elements | 1270 | — |
| Macrocells | 980 | — |
| User I/Os | 114 | — |
| Maximum Internal Frequency | 118.3 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 6.2 ns | — |
| Internal Frequency (typical) | 201 MHz | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Configuration Memory | Flash (non-volatile, in-system programmable) | — |
| VCCINT (Core Supply) | 1.71 V to 1.89 V | — |
| VCCIO (I/O Supply, per bank) | 1.2 V to 3.3 V | — |
| Number of I/O Banks | 4 | — |
| Supported I/O Standards | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins | — |
| JTAG Interface | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) | — |
| Programming Interface | JTAG in-system programmable (Altera Quartus II) | — |
| Program/Erase Cycles | Up to 100,000 | — |
| Boîtier | TQFP-144 (22 x 22 mm, 0.5 mm pitch) | 144-pin TQFP (T144) |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | 0 C to +85 C (commercial grade) | -40C to +100C (Industrial) |
| Statut RoHS | Compliant | — |
| Family | — | MAX V |
| Device Logic Elements | — | 980 |
| Number of Macro Cells | — | 980 |
| Maximum User I/O Pins | — | 212 |
| Number of Logic Array Blocks (LABs) | — | 61 |
| User Flash Memory | — | 8 Kbits |
| Maximum Operating Frequency | — | 201.1 MHz |
| Pin-to-Pin Delay (tPD) | — | 1.5 ns (max) |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V (multi-voltage) |
| Configuration Method | — | Non-volatile flash, in-system programmable |
| Programmable Via | — | JTAG (IEEE 1149.1) / Quartus Prime |