5M1270ZT144C5N vs 5M160ZM68C5N Comparaison
Comparaison détaillée côte à côte de 5M1270ZT144C5N par Altera et 5M160ZM68C5N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ Actif
Comparaison des spécifications
| Paramètre | 5M1270ZT144C5N | 5M160ZM68C5N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $12,45 | $3,12 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Series | MAX V | 5M160Z |
| Logic Elements | 1270 | — |
| Macrocells | 980 | 128 |
| User I/Os | 114 | — |
| Maximum Internal Frequency | 118.3 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 6.2 ns | — |
| Internal Frequency (typical) | 201 MHz | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Configuration Memory | Flash (non-volatile, in-system programmable) | Non-volatile flash (instant-on, no boot PROM required) |
| VCCINT (Core Supply) | 1.71 V to 1.89 V | — |
| VCCIO (I/O Supply, per bank) | 1.2 V to 3.3 V | — |
| Number of I/O Banks | 4 | — |
| Supported I/O Standards | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins | — |
| JTAG Interface | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) | — |
| Programming Interface | JTAG in-system programmable (Altera Quartus II) | JTAG (IEEE Std. 1149.1), in-system programmable |
| Program/Erase Cycles | Up to 100,000 | — |
| Boîtier | TQFP-144 (22 x 22 mm, 0.5 mm pitch) | — |
| Type de montage | Surface Mount | — |
| Température de fonctionnement | 0 C to +85 C (commercial grade) | — |
| Statut RoHS | Compliant | Compliant |
| Family | — | MAX V CPLD |
| Logic Elements (typical) | — | 160 |
| Maximum Operating Frequency | — | 118.3 MHz |
| Pin-to-Pin Logic Delay | — | 7.5 ns |
| Number of Logic Array Blocks (LABs) | — | 4 |
| User Flash Memory | — | 8 Kbits |
| Core Supply Voltage | — | 1.8 V |
| I/O Standards Supported | — | LVTTL, LVCMOS 1.5/1.8/2.5/3.3 V |
| Package Type | — | 68-ball Micro FineLine BGA (MBGA) |
| Plage de température de fonctionnement | — | 0C to +85C (commercial) |
| Internal Oscillator | — | Yes (on-chip) |
| Lead-Free | — | Yes |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |