A42MX16-2PLG84I vs A42MX24-2PLG84I Comparaison
Comparaison détaillée côte à côte de A42MX16-2PLG84I par Microchip Technology et A42MX24-2PLG84I par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
A42MX16-2PLG84I - 24K Gate MX FPGA, 84-PLCC | Microchip
A42MX16-2PLG84I ✓ ActifMicrochip Technology
A42MX24-2PLG84I - 36K Gate Antifuse FPGA, 84-PLCC | Microchip
A42MX24-2PLG84I ✓ ActifComparaison des spécifications
| Paramètre | A42MX16-2PLG84I | A42MX24-2PLG84I |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $30,80 | $55,40 |
| System Gates | 24000 | 36000 gates |
| Family | MX FPGA | MX (42MX) |
| Number of I/O | 72 | — |
| Speed Grade | -2 | -2 |
| Supply Voltage (Core) | 3 V to 3.6 V | — |
| Supply Voltage (I/O) | 4.5 V to 5.5 V | — |
| Température de fonctionnement | -40C to +85C | -40C to +85C (Industrial) |
| Programmability | One-Time Programmable (antifuse) | One-Time Programmable (antifuse) |
| Boîtier | 84-LCC (J-Lead / PLCC) | 84-PLCC (J-Lead) |
| Type de montage | Surface Mount | Surface Mount |
| Configuration Memory | Internal (no external boot PROM required) | — |
| Statut RoHS | Lead Free | Lead Free (per Kynix listing) |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL level] | — |
| Total Logic Modules | [DATA_NEEDED: logic module count] | — |
| Max User Flip-Flops | [DATA_NEEDED: flip-flop count] | — |
| Embedded Memory | None (logic only, MX16 fabric) | — |
| Development Software | Microchip Libero SoC | — |
| Logic Cells | — | 912 cells |
| User I/O | — | 72 |
| Technology | — | 0.45 um antifuse |
| Core Architecture Voltage | — | 5.0 V |
| I/O Voltage Support | — | 3.3 V / 5.0 V mixed |
| Configuration | — | No external boot device required |
| Dedicated Decode Blocks | — | D-modules (wide-input AND, CPLD-like) |
| Packaging | — | Tray |
| Primary Applications | — | ASIC alternative, legacy PLD integration |