AD677BD vs AD677AD Comparaison
Comparaison détaillée côte à côte de AD677BD par Analog Devices et AD677AD par Analog Devices. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | AD677BD | AD677AD |
|---|---|---|
| Marque | Analog Devices | Analog Devices |
| Catégorie | ADC/DAC | ADC/DAC |
| Statut du cycle de vie | Dernier achat | Dernier achat |
| Converter Type | 16-bit sampling ADC | — |
| Architecture | Switched-capacitor charge-redistribution SAR | — |
| Résolution | 16 bit | 16 bit |
| Fréquence d'échantillonnage | 100 kSPS | 100 kSPS |
| Total Conversion Time | 10 µs | 10 us |
| Input Count | 1 analog input | 1 analog input |
| Type de sortie | Serial | Serial |
| Analog Supply | +5 V and ±12 V | — |
| Digital Supply | Separate 5 V digital supply | — |
| Typical Power Consumption | 450 mW during conversion with 10 V reference | — |
| Typical Power Consumption with 5 V Reference | 360 mW during conversion | — |
| On-Chip Calibration | Digital autocalibration corrects internal nonlinearities | — |
| Boîtier | 16-pin ceramic DIP | 16-lead ceramic DIP (CDIP) |
| Type de montage | Through-hole | Through-hole |
| Lead Pitch | 2.54 mm | — |
| Package Width | 7.62 mm | — |
| Analog Devices Family Temperature Range | 0 °C to +70 °C commercial or -40 °C to +85 °C industrial | — |
| Plage de tension d'entrée | [DATA_NEEDED: AD677BD input voltage range] | [DATA_NEEDED: Input voltage range] |
| Reference Voltage Range | [DATA_NEEDED: AD677BD reference voltage range] | — |
| Integral Nonlinearity | [DATA_NEEDED: AD677BD integral nonlinearity] | [DATA_NEEDED: Integral nonlinearity] |
| SNR | [DATA_NEEDED: AD677BD signal-to-noise ratio] | [DATA_NEEDED: Signal-to-noise ratio] |
| ENOB | [DATA_NEEDED: AD677BD effective number of bits] | — |
| Statut RoHS | [DATA_NEEDED: AD677BD RoHS status] | [DATA_NEEDED: RoHS status] |
| ADC Architecture | — | Successive-approximation-register (SAR) |
| Internal Architecture | — | Switched-capacitor charge redistribution |
| Calibration | — | On-chip autocalibration with digital nonlinearity correction |
| Tension de référence | — | [DATA_NEEDED: External reference voltage] |
| Analog Input Type | — | [DATA_NEEDED: Unipolar or bipolar input configuration] |
| Effective Number of Bits | — | [DATA_NEEDED: Effective number of bits] |
| Input Impedance | — | [DATA_NEEDED: Input impedance] |
| Input Sampling Capacitance | — | [DATA_NEEDED: Input sampling capacitance] |
| Digital Interface Levels | — | [DATA_NEEDED: Digital logic input and output levels] |
| Serial Clock Frequency | — | [DATA_NEEDED: Maximum serial clock frequency] |
| Plage de température de fonctionnement | — | [DATA_NEEDED: Operating temperature range] |
| Supply Voltage Range | — | [DATA_NEEDED: Supply voltage range] |
| Power Consumption | — | [DATA_NEEDED: Typical and maximum power consumption] |
| Package Dimensions | — | [DATA_NEEDED: Ceramic DIP package dimensions] |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Lead-Free Status | — | [DATA_NEEDED: Lead-free status] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |