ADS6225IRGZR vs ADS6223IRGZR Comparaison
Comparaison détaillée côte à côte de ADS6225IRGZR par Texas Instruments et ADS6223IRGZR par Texas Instruments. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | ADS6225IRGZR | ADS6223IRGZR |
|---|---|---|
| Marque | Texas Instruments | Texas Instruments |
| Catégorie | ADC/DAC | ADC/DAC |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $24,10 | $21,40 |
| Résolution | 12 bit | 12 bit |
| Number of Channels | 2 | 2 |
| Sample Rate (max) | 125 MSPS | — |
| Architecture | Pipelined | Pipelined |
| Analog Input Type | Differential / Single-ended | — |
| Output Interface | Serialized LVDS (1-wire / 2-wire) | — |
| Analog Supply Voltage | 3.3 V (AVDD) | 3.3 V (typical) |
| Digital I/O Supply | 3.3 V (DVDD) | — |
| Input Bandwidth | [DATA_NEEDED: input bandwidth MHz] | — |
| SNR | [DATA_NEEDED: SNR dBFS at Nyquist] | — |
| SFDR | [DATA_NEEDED: SFDR dBc at Nyquist] | — |
| ENOB | [DATA_NEEDED: effective number of bits] | — |
| Power Dissipation | [DATA_NEEDED: power consumption mW at 125 MSPS] | — |
| Gain Coarse / Fine | 3.5 dB coarse, up to 6 dB programmable fine gain | — |
| Reference | Internal / External (selectable) | — |
| Température de fonctionnement | -40C to +85C (industrial) | -40C to +85C |
| Boîtier | 48-pin VQFN (RGZ), 7x7 mm with exposed pad | — |
| Type de montage | Surface Mount | Surface Mount |
| Niveau MSL | 3 (168 hours) | [DATA_NEEDED: MSL rating] |
| Statut RoHS | Compliant | Compliant |
| Family Compatibility | Pin-compatible with ADS6224/ADS6223/ADS6222 (lower-speed variants); feature-compatible with 14-bit ADS624X family and quad ADS642X/ADS644X families | — |
| Manufacturer | — | Texas Instruments |
| Part Number | — | ADS6223IRGZR |
| Description | — | Dual-Channel, 12-Bit, 65/80/105/125 MSPS ADC with Serial LVDS Interface |
| Sample Rate (Max) | — | 125 MSPS |
| Sample Rate (This Variant) | — | 80 MSPS |
| Data Interface | — | Serial LVDS (1-Wire / 2-Wire) |
| Digital Supply Voltage | — | 3.3 V (typical) |
| Input Type | — | Differential |
| Coarse Gain | — | 3.5 dB |
| Programmable Fine Gain | — | 0 to 6 dB |
| Simultaneous Sampling | — | Yes (two sample-and-hold stages) |
| Boîtier / Format | — | 48-VFQFN Exposed Pad (RGZ) |
| No. of Terminals | — | 48 |
| Terminal Form | — | No Lead |
| Package Code | — | HVQCCN |
| Lead Free | — | Yes |
| Statut du cycle de vie | — | Active |