ATSAMA5D225C-D1M-CU vs ATSAMA5D22B-CU Comparaison
Comparaison détaillée côte à côte de ATSAMA5D225C-D1M-CU par Microchip Technology et ATSAMA5D22B-CU par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
ATSAMA5D225C-D1M-CU - 500MHz Cortex-A5 MPU w/ 128Mb DDR2 SiP | Microchip
ATSAMA5D225C-D1M-CU ✓ ActifMicrochip Technology
ATSAMA5D22B-CU - 500MHz ARM Cortex-A5 MPU, 196-TFBGA | Microchip
ATSAMA5D22B-CU ✓ ActifComparaison des spécifications
| Paramètre | ATSAMA5D225C-D1M-CU | ATSAMA5D22B-CU |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | Microcontrollers | Microcontrollers |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $12,60 | $10,75 |
| Core Processor | ARM Cortex-A5 | ARM Cortex-A5 (32-bit, single core) |
| Number of Cores | 1 Core, 32-Bit | — |
| Maximum CPU Clock | 500 MHz | 500 MHz |
| Integrated DRAM | 128 Mbit DDR2 SDRAM (SiP) | — |
| ROM / Boot Code | 160 KB ROM | — |
| Graphics Acceleration | Yes (LCD controller up to WXGA 1366x768) | — |
| RAM Controllers | LPDDR1, LPDDR2, LPDDR3, DDR2, DDR3, DDR3L, QSPI | — |
| Ethernet | 10/100/1000 GMAC | — |
| USB | 1x HSIC, 1x USB 2.0 HS Host/Device | — |
| CAN | CAN-FD | — |
| Security | Arm TrustZone, secure boot, tamper detection, AES/SHA/TRNG | — |
| Touch Controller | Peripheral Touch Controller (PTC) integrated | — |
| Audio | Embedded audio subsystem (I2S, Class-D amplifier) | — |
| Boîtier | 196-ball TFBGA 11x11 mm, 0.8 mm pitch | 196-TFBGA (CSBGA), 11x11 mm, 0.8 mm pitch |
| Température de fonctionnement | -40C to +85C (Industrial, IND TEMP) | -40 C to +85 C (industrial) |
| Tension d'alimentation | 1.2 V core (per typical SiP) | — |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Statut RoHS | Compliant (Green, lead-free) | Compliant |
| Core Architecture | — | ARMv7-A with TrustZone and NEON |
| L1 Instruction Cache | — | 32 Kbytes |
| L1 Data Cache | — | 32 Kbytes |
| L2 Cache / SRAM | — | 128 Kbytes (configurable as internal SRAM) |
| Memory Architecture | — | MMU (full virtual memory support) |
| External Memory Support | — | LPDDR1, LPDDR2, LPDDR3, DDR2, DDR3, DDR3L (16-bit) |
| Flash Interfaces | — | 2x QSPI, e.MMC |
| Supply Voltage (core) | — | 1.2 V (typ, internal regulator) |
| Supply Voltage (I/O) | — | 3.3 V (typ) |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |
| Lead-Free / Halogen-Free | — | Lead-free finish; halogen status [DATA_NEEDED] |