ATSAMA5D28A-CU vs ATSAMA5D27A-CNR Comparaison
Comparaison détaillée côte à côte de ATSAMA5D28A-CU par Microchip Technology et ATSAMA5D27A-CNR par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
ATSAMA5D28A-CU - ARM Cortex-A5 500MHz MPU, 289-LFBGA | Microchip
ATSAMA5D28A-CU ✓ ActifMicrochip Technology
ATSAMA5D27A-CNR - 500MHz Cortex-A5 MPU, 289-LFBGA | Microchip
ATSAMA5D27A-CNR ✓ ActifComparaison des spécifications
| Paramètre | ATSAMA5D28A-CU | ATSAMA5D27A-CNR |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | Microcontrollers | Microcontrollers |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $14,85 | $10,95 |
| Core Architecture | ARM Cortex-A5 (32-bit) | — |
| Maximum CPU Clock | 500 MHz | 500 MHz |
| Number of Cores | 1 | 1 Core, 32-Bit |
| SIMD Engine | ARM NEON | — |
| Floating-Point Unit | Yes (VFPv4) | — |
| Instruction Set | ARMv7-A | — |
| On-chip ROM | 160 KB (secure boot) | — |
| External Memory Support | DDR2 / DDR3L / LPDDR2 / LPDDR3 (16-bit, with ECC) | — |
| Flash Interface | QSPI, e.MMC, SD | — |
| Boîtier | 289-LFBGA (14x14 mm) | 289-LFBGA, 14x14 mm |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | -40C to +85C (industrial grade per -CU suffix) | -40C to +105C (industrial) |
| Supply Voltage (Core) | 1.2 V | — |
| LCD Controller | Yes (with touch-screen support) | — |
| Cryptography | AES, SHA, secure boot (TRNG + AES-OTF) | — |
| Ethernet | 10/100 Mbps MAC with PHY interface | 10/100 Mbps (1x EMAC) with IEEE 1588 |
| USB | USB 2.0 Host + Device with on-chip PHY | USB 2.0 + HSIC |
| CAN | CAN-FD | CAN, CAN-FD (1) |
| ADC | 12-bit, multi-channel | — |
| Statut RoHS | Compliant | Compliant |
| Niveau MSL | [DATA_NEEDED: MSL level] | 3 |
| Core Processor | — | ARM Cortex-A5 |
| Instruction Set Architecture | — | ARMv7-A with Neon, MPE |
| Graphics Acceleration | — | Yes (2D Graphics LCD Controller, GLCDC) |
| L1 Cache | — | 32 KB I-cache + 32 KB D-cache |
| L2 Cache | — | 128 KB |
| External Memory Controller | — | DDR2, DDR3L, LPDDR2, LPDDR3, QSPI, e.MMC Flash |
| Display Interface | — | Keyboard, LCD, Touchscreen (24-bit GLCDC) |
| Hardware Cryptography | — | AES-128/256, secure boot, TRNG, tamper pins |
| I/O Voltage | — | 3.3 V |
| Delivery Form | — | Tape & Reel (TR) |