CDK2307AILP64 vs CDK2307BILP64 Comparaison
Comparaison détaillée côte à côte de CDK2307AILP64 par Cadeka et CDK2307BILP64 par MaxLinear. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | CDK2307AILP64 | CDK2307BILP64 |
|---|---|---|
| Marque | Cadeka | MaxLinear |
| Catégorie | ADC/DAC | ADC/DAC |
| Statut du cycle de vie | Actif | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,10 | $9,28 |
| Manufacturer | Cadeka Microcircuits (MaxLinear) | MaxLinear (formerly Exar / Cadeka) |
| Part Number | CDK2307AILP64 | — |
| Description | Dual 12/13-bit 20/40/65/80 MSPS Analog-to-Digital Converter | Dual ADC, Pipelined, 12/13-bit, 40 MSPS |
| Résolution | 13 bit (12-bit option via CDK2308 family) | 12-bit or 13-bit (selectable) |
| Sampling Rate (this variant) | 20 MSPS | — |
| Sampling Rate (family max) | 80 MSPS (CDK2307AILP64 = 20 MSPS grade) | — |
| Number of Channels | 2 (dual, simultaneous sampling) | 2 |
| Input Type | Single-ended analog input | [DATA_NEEDED: input type - single-ended / differential] |
| Output Interface | Parallel CMOS | CMOS, Parallel |
| Core Supply Voltage | 1.8 V | — |
| I/O Supply Voltage | 1.7 V to 3.6 V | — |
| Power Dissipation | 30 mW at 20 MSPS; 55/85/102 mW at 40/65/80 MSPS | — |
| Reference | Internal (bandgap, integrated) | — |
| Boîtier | 64-pin QFN (LP64) with exposed pad, 9x9 mm | — |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | -40C to +85C (industrial) [DATA_NEEDED: exact temp grade] | — |
| Pin Compatibility | Pin-compatible with CDK2308 family (12-bit variant) | — |
| Statut RoHS | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Part Status | — | Not Recommended for New Designs (NRND) per IC-Acquisition listing |
| Sample Rate | — | 40 MSPS |
| Family Sample Rates | — | 20 / 40 / 65 / 80 MSPS (family options) |
| Architecture | — | Pipelined with digital error correction |
| Reference Type | — | Internal |
| Control Interface | — | CMOS control logic |
| Boîtier / Format | — | 64-pin QFN-EP (9x9 mm) |
| Supplier Device Package | — | 64-QFN (9x9) with Exposed Pad |
| Packaging | — | Tray |
| Plage de température de fonctionnement | — | [DATA_NEEDED: operating temperature range] |