EP1C12Q240C7N vs EP1C12Q240C6N Comparaison
Comparaison détaillée côte à côte de EP1C12Q240C7N par Intel et EP1C12Q240C6N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1C12Q240C7N | EP1C12Q240C6N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $22,80 | $119,00 |
| Family | Cyclone | — |
| Series | Cyclone I | — |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 12,060 | — |
| Configurable Logic Blocks (CLBs) | 12,060 | — |
| Total RAM Bits | 239,616 bits | 239616 |
| Embedded Memory Blocks | 52 M4K blocks (4 Kbit each) | — |
| Maximum User I/O | 173 | — |
| Process Technology | 130 nm CMOS | 130 nm |
| Core Voltage | 1.5 V | — |
| Internal Performance | 320.1 MHz | — |
| Speed Grade | C7 (commercial, -7) | — |
| Température de fonctionnement | 0C to +85C (commercial) | — |
| Boîtier | 240-pin PQFP / BFQFP | 240-pin PQFP/BFQFP (34.6 x 34.6 mm, 0.5 mm pitch) |
| Package Body Size | 34.60 x 34.60 mm | — |
| Lead Pitch | 0.50 mm | — |
| Terminal Form | Gull wing | — |
| Type de montage | Surface Mount | Surface Mount |
| PLLs | 2 (dual-clock) | — |
| Configuration Method | SRAM, serial/parallel via external flash | — |
| Product Family | — | Cyclone FPGA (Intel/Altera) |
| Number of Logic Elements | — | 12060 |
| Number of M4K Blocks | — | 52 |
| Number of User I/Os | — | 173 |
| Maximum Internal Clock (speed grade -6) | — | 320.1 MHz |
| Core Supply Voltage | — | 1.5 V |
| I/O Supply Voltage Options | — | [DATA_NEEDED: supported I/O standards list] |
| Temperature Grade | — | Commercial (C suffix) |
| Configuration Type | — | SRAM-based, in-circuit programmable |
| RoHS Lead-Free Finish | — | Yes (N suffix) |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |
| JTAG Boundary Scan | — | Supported |