EP1S10B672C7 vs EP1S10F672C6 Comparaison
Comparaison détaillée côte à côte de EP1S10B672C7 par Intel et EP1S10F672C6 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1S10B672C7 | EP1S10F672C6 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $140,00 | $72,00 |
| Manufacturer | Intel (formerly Altera) | — |
| Series | Stratix | Stratix® I |
| Logic Elements | 10,570 | — |
| Embedded Memory (Total) | 920 Kbits | — |
| DSP Blocks | Yes (DSP multiplier blocks) | 6 |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | — |
| Process Technology | 0.13 µm CMOS | 130 nm CMOS |
| Supply Voltage (Core) | 1.5 V | — |
| Package Type | 672-ball FineLine BGA | — |
| Package Dimensions | 35 x 35 mm | — |
| Ball Pitch | 1.27 mm | — |
| Logic Family | CMOS | — |
| Température de fonctionnement | 0 °C to 85 °C (Commercial) | 0C to +85C (Commercial) |
| Temperature Grade | Commercial (C) | — |
| Speed Grade | 7 | — |
| Configuration Method | JTAG / EPC serial configuration | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Family | — | Stratix FPGA |
| Logic Elements (LE) | — | 10,570 |
| Logic Array Blocks (LABs) | — | 1057 |
| Total Memory Bits | — | 920,448 bits |
| Embedded Memory | — | TriMatrix (MRAM/M4K) |
| Number of I/Os | — | 345 |
| Number of PLLs | — | 12 (6 per device side) |
| Core Voltage | — | 1.5 V |
| Boîtier | — | 672-ball FineLine BGA (FBGA) |
| Maximum Core Frequency | — | 420.17 MHz |
| Configuration Modes | — | Passive Serial (PS), Fast Passive Parallel (FPP), Active Serial (AS) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |