EP1S10B672C7N vs EP1S10B672C6 Comparaison
Comparaison détaillée côte à côte de EP1S10B672C7N par Intel et EP1S10B672C6 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1S10B672C7N | EP1S10B672C6 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $67,90 | $185,00 |
| Manufacturer | Intel / Altera | Intel / Altera |
| Product Family | Stratix | — |
| Logic Family | CMOS | CMOS |
| Logic Elements/Cells | 10570 cells | — |
| Maximum Internal Clock | 420.17 MHz | — |
| Core Supply Voltage | 1.5 V | — |
| Technology Node | 130 nm | — |
| Package Code | BGA | — |
| Number of Terminals | 672 | — |
| Package Body Size | 35 x 35 mm | — |
| Ball Pitch | 1.27 mm | — |
| Package Shape | Square | — |
| Temperature Grade | Commercial extended, 0 to 85 C | — |
| Terminal Form | Ball | — |
| Configuration/JTAG | JTAG boundary-scan per Stratix family data sheet | — |
| Number of User I/O in 672-BGA | [DATA_NEEDED: user I/O count] | — |
| Total RAM Bits | [DATA_NEEDED: total RAM bits] | — |
| Embedded PLLs | [DATA_NEEDED: PLL count] | — |
| Config Device Compatibility | [DATA_NEEDED: supported configuration devices] | — |
| RoHS | unknown - N suffix may indicate Pb-free, not verified in fetched data | — |
| Series | — | Stratix |
| Logic Elements / Cells | — | 10,570 |
| LABs / CLBs | — | 1,057 |
| User I/Os | — | 345 |
| Boîtier | — | 672-BBGA (35 x 35 mm, 1.27 mm pitch) |
| Supply Voltage (Core) | — | 1.5 V (1.425 V - 1.575 V) |
| Process Technology | — | 130 nm CMOS |
| Maximum Operating Frequency | — | 450.05 MHz |
| Température de fonctionnement | — | 0 C to 85 C (Commercial Extended) |
| Type de montage | — | Surface Mount (BGA) |
| Supplier Device Package | — | 672-BGA |
| Memory | — | Embedded TriMatrix (MRAM/M4K) blocks |
| DSP Blocks | — | Yes, dedicated multiply-accumulate blocks |
| Clock Management | — | PLLs for clock synthesis |
| Configuration | — | JTAG / passive serial / fast passive parallel |
| Statut RoHS | — | Compliant |