EP1S10F672I7N vs EP1S10F672C6 Comparaison
Comparaison détaillée côte à côte de EP1S10F672I7N par Intel et EP1S10F672C6 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1S10F672I7N | EP1S10F672C6 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $118,00 | $72,00 |
| Family | Stratix | Stratix FPGA |
| Logic Elements | 10,570 | — |
| Logic Array Blocks (LABs) | 1,057 | 1057 |
| User I/Os | 345 | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Core Supply Voltage | 1.5 V | — |
| Maximum Internal Frequency | 420.17 MHz | — |
| Température de fonctionnement | 0C to 85C | 0C to +85C (Commercial) |
| Boîtier | 672-ball FineLine BGA, 35 x 35 mm, 1.27 mm pitch | 672-ball FineLine BGA (FBGA) |
| Logic Family | CMOS | — |
| Embedded Memory | 920 Kbits (TriMatrix) | TriMatrix (MRAM/M4K) |
| DSP Blocks | Yes (dedicated) | 6 |
| Configuration Interface | Active Serial / Passive Serial / JTAG | — |
| JTAG Support | IEEE 1149.1 boundary-scan | IEEE 1149.1 boundary-scan |
| Speed Grade | I7 (industrial, -7 speed bin) | — |
| Niveau MSL | 3 (per JEDEC J-STD-020, typical for BGA of this era) | — |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Statut RoHS | [DATA_NEEDED: per Intel PDN] | [DATA_NEEDED: RoHS status] |
| Series | — | Stratix® I |
| Logic Elements (LE) | — | 10,570 |
| Total Memory Bits | — | 920,448 bits |
| Number of I/Os | — | 345 |
| Number of PLLs | — | 12 (6 per device side) |
| Core Voltage | — | 1.5 V |
| Maximum Core Frequency | — | 420.17 MHz |
| Configuration Modes | — | Passive Serial (PS), Fast Passive Parallel (FPP), Active Serial (AS) |