EP1S25F780C5 vs EP1S25F780I6N Comparaison
Comparaison détaillée côte à côte de EP1S25F780C5 par Altera et EP1S25F780I6N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP1S25F780C5 - Stratix I FPGA, 25,660 LEs, 597 I/O, 780-FBGA | Altera / Intel
EP1S25F780C5 ⚠ Dernier achatIntel
EP1S25F780I6N - Stratix 25,660-LE FPGA, 780-BBGA, Industrial | Altera/Intel
EP1S25F780I6N ObsoleteComparaison des spécifications
| Paramètre | EP1S25F780C5 | EP1S25F780I6N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 249,50 | $1 250,00 |
| Family | Stratix I | Stratix |
| Logic Elements | 25,660 | 25,660 |
| Logic Array Blocks (LABs) | 2,566 | 2,566 |
| Total RAM Bits | 1,944,576 | 1,944,576 |
| Embedded Multipliers (DSP blocks) | 80 (typical) | — |
| User I/O Count | 597 | — |
| Boîtier | 780-FBGA (29x29 mm) | 780-BBGA (FineLine BGA, 29 x 29 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | 1.425 V to 1.575 V | — |
| Speed Grade | C5 | 6 (I6 - industrial) |
| Operating Temperature (TJ) | 0 °C to +85 °C (commercial) | — |
| Process Technology | 0.13 µm CMOS, SRAM-based | 130 nm CMOS |
| LVDS Performance | Up to 7.6 Gbps (claim per family datasheet) | — |
| PLLs | Up to 8 per device | — |
| Global Clock Networks | 14 | — |
| Type de montage | Surface Mount (SMT, BGA) | Surface Mount (BGA) |
| Statut RoHS | Compliant per Altera product page | [DATA_NEEDED: rohs status] |
| User I/O Pins | — | 597 |
| Core Voltage | — | 1.5 V |
| Température de fonctionnement | — | 0C to 85C (industrial) |
| Niveau MSL | — | 3 (per Partstack listing) |
| Lead Free | — | Yes (per Ampheo listing) |
| DSP Blocks | — | Yes (dedicated 9/18/36-bit multipliers) |
| Embedded PLL | — | Yes |
| LVDS Support | — | Yes (up to 840 Mbps per Altera datasheet family) |
| Configuration Mode | — | JTAG / Passive Serial / Fast Passive Parallel (per Stratix family) |