EP1S40F1020C5DM vs EP1S40F1020C5GA Comparaison
Comparaison détaillée côte à côte de EP1S40F1020C5DM par Intel et EP1S40F1020C5GA par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1S40F1020C5DM | EP1S40F1020C5GA |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $198,00 | $171,00 |
| Product Type | FPGA - Field Programmable Gate Array | — |
| Series | Stratix | Stratix |
| Logic Elements | 41,250 | — |
| Embedded Memory | 3,423 Kbits TriMatrix | — |
| User I/O Count | 773 | 773 |
| Number of LABs/CLBs | 4125 | — |
| DSP Blocks | 12 (up to 28.8 GMACS at 200 MHz) | Embedded multiplier blocks (count per Stratix datasheet family) |
| Number of PLLs | 6 (8 outputs each) | — |
| Number of Clock Networks | 16 | — |
| Boîtier | 1020-ball FineLine BGA (33 mm x 33 mm, 1.0 mm pitch) | 1020-BBGA (FineLine BGA) |
| Core Voltage VCCINT | 1.5 V | — |
| I/O Voltage VCCIO | 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) | — |
| Process Technology | 0.13 µm CMOS | — |
| Température de fonctionnement | 0C to +85C (commercial) | 0C to +85C (Commercial) |
| Configuration Modes | PS, PPS, PPA, JTAG | — |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Unknown - non-GA suffix commercial part |
| Niveau MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| Logic Elements (LE) | — | 41,250 |
| Total RAM Bits | — | 3,423,744 |
| Speed Grade | — | C5 |
| Process Node | — | 0.13 µm CMOS with 9-layer metal |
| Supply Voltage (Core) | — | [DATA_NEEDED: VCCINT value] |
| I/O Bank Count | — | [DATA_NEEDED: bank count] |
| PLL Count | — | Up to 12 enhanced PLLs (per Stratix family) |
| High-Speed Transceivers | — | Up to 12 channels (per Stratix family, variant dependent) |
| Configuration Method | — | JTAG, Passive Serial, Altera EPC device |
| Lead-Free | — | Yes (per Altera/Intel policy at release) |